In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of circuits derived from sum of products and product of sums expressions for a given combinational logic function are investigated to determine the testability of FET stuck-open faults by tests which will remain valid in the presence of arbitrary circuit delays. Necessary and sufficient conditions for the existence of tests that will remain valid in the presence of arbitrary circuit delays are derived. Using these conditions, it is shown that all single FET stuck-open faults, in a specific design using a single CMOs complex gate, are detectable by tests that remain valid in the presence of arbitrary circuit delays. For several other realizations, methods to augment them, to insure detectability of all single FET stuck-open faults by tests that will remain valid in the presence of arbitrary circuit delays are proposed. It is observed that in many of the logic circuits investigated it is also possible to avoid test invalidation due to charge distribution.

Due to inaccuracies in gate level models of VLSI digital circuits, current practice is to use transistor level simulators to analyze VLSI digital circuits. The inaccuracies of gate level models are even more severe when faults in digital circuits are considered. For this reason, recently several researchers have proposed the use of test pattern generation from digital circuits described at the transistor level. In this paper an efficient test pattern generation procedure for digital circuits described at the transistor level is given.