This article presents a 6-bit, 3.6-GS/s, 4-channel time-interleaved (TI) analog-to-digital converter (ADC) with a front-rank most significant bit (MSB) decision (FRMD) technique and a 2-then−1.5-bit/cycle successive approximation register (SAR) architecture. The proposed FRMD technique determines the MSB concurrently with sampling, enhancing the conversion speed of the sub-ADCs. The proposed 2-then−1.5-bit/cycle architecture, which aligns well with the FRMD technique, incorporates comparator background offset calibration without consuming extra cycles, zeroing the offset. Since the comparator offset is the dominant source of inter-channel offset mismatch in TI-ADCs, this approach naturally eliminates the need for extra inter-channel offset calibration. A prototype ADC was fabricated in a 28-nm CMOS process, achieving 33.9 dB signal-to-noise-and-distortion ratio (SNDR) and 49.8 dB spurious-free dynamic range (SFDR) at the Nyquist frequency. The ADC consumes 6.15 mW at 3.6 GS/s, resulting in a Walden figure of merit (FoMW) of 41.8 fJ/conversion-step.

This paper presents a 50 Gb/s four-level pulse amplitude modulation 4 (PAM-4) wireline transceiver that incorporates a high-swing PAM-4 driver in the transmitter (TX) and an integrator-based baud-rate linear clock and data recovery (IB-CDR) in the receiver (RX). The PAM-4 driver in the TX employs two types of non-return to zero (NRZ)-current mode logic (CML) drivers. The proposed architecture overcomes the inherent signal-to-noise ratio (SNR) limitations of PAM-4 by generating signal amplitudes greater than the supply voltage (VDD). The RX features an IB-CDR that can determine the phase difference between the PAM-4 signal and the sampling clock using the sign and magnitude of the integrators. Consequently, because the IB-CDR can reduce the requirement for additional threshold voltages and samplers for CDR operation, the RX can achieve a competitive Figure-of-Merit with reduced hardware overhead. Moreover, a dual-loop analog equalizer (DAEQ) is introduced to mitigate inter-symbol interference between the TX and RX. In the DAEQ, one loop increases the peak gain, while another loop controls the system bandwidth. The proposed TX and RX were fabricated using a 28 nm CMOS technology and has a maximum data rate of 50 Gb/s. The prototype with a total area of 0.18 mm2 enables a bit error rate of$10^{-11}$at 15.3 dB attenuation and has a power efficiency of 3.28 pJ/bit.

This study proposes a power-efficient 28-Gb/s single-ended four-level pulse amplitude modulation (PAM-4) transceiver (TRX) for next-generation memory interfaces. In the transmitter (TX), an active-inductor equalizer (EQAI) is utilized, while in the receiver (RX), an amplitude-detection least significant bit (LSB) decoder is employed. In the TX, conventional equalization techniques consume substantial power owing to the inclusion of additional components and strong driving power required to mitigate channel-induced intersymbol interference (ISI). However, the proposed EQAI achieves a bandwidth extension up to the Nyquist frequency through gain boosting while reducing hardware costs and minimizing the driving strength. This results in a simple structure with operational efficiency, facilitating low power consumption and a compact area compared with conventional TX equalizers. In PAM-4 RX, the power dissipation is proportional to the clock buffer and the number of comparators used for data decoding. To improve the hardware cost and the power usage in the RX, the proposed RX design utilizes an amplitude-detection LSB decoder, which reduces the number of comparators and comprises a one-stage structure by detecting the amplitude differences between the reference and input voltages during LSB decoding. This ensures the hardware cost and power consumption improvement while implementing a one-tap direct decision feedback equalizer (DFE). The TRX for memory interfaces is optimized for low-power performance by employing these methods, resulting in a notable energy efficiency of 0.96 pJ/bit. This structure is fabricated using a 28-nm CMOS technology, and the core area of the TRX occupies 0.0053 mm2.

This paper presents a 25-Gb/s single-ended four-level pulse amplitude modulation (PAM-4) transmitter (TX) with an integrated pulse width modulation (iPWM)-based feed-forward equalizer (FFE) and a ratio of level mismatch (RLM)-matched voltage-mode driver for high-speed memory interfaces. The phase-domain iPWM-based PAM-4 FFE is proposed to minimize the input/output (I/O) capacitance by equalizing the PAM-4 data in advance of the pre-driver. The TX bandwidth is increased while achieving superior energy efficiency. Moreover, the RLM-matched voltage-mode PAM-4 driver with a ZQ calibration is proposed to compensate for the impedance variation from the four output levels and improve the output linearity. An RLM control pull-up transistor in the proposed driver obviates the need for a data encoder or passive resistors to improve the RLM and occupies a small area. The proposed single-ended PAM-4 TX was fabricated in a 28-nm CMOS technology and occupies 0.005 mm2. It achieves 0.43 pJ/b at 25 Gb/s and an RLM of 99.3%.

This paper proposes a fully integrated dual-output continuously scalable-conversion-ratio (CSCR) switched-capacitor (SC) converter that increases the overall power conversion efficiency (PCE) beyond that of the conventional dual-output SC converters. The structure employs proposed dual-output CSCR SC stage and channel SC stage to transfer charges to two output load voltages ($V_{\mathrm{OUT}}$s) with high PCE. Also, the converter is controlled by analog switching frequency modulation (ASFM) and digital flying capacitance modulation (DFCM) loops to regulate both$V_{\mathrm{OUT}}$s simultaneously. The proposed converter is fabricated using a 180 nm CMOS process, and regulates$V_{\mathrm{OUT}}$of 1.1–1.6 V and 0.55–0.95 V with an input voltage of 1.5–1.9 V. In measurement, the proposed converter achieves a maximum PCE of 85%, and an average PCE of 78.6% for the available$V_{\mathrm{OUT}}$ranges. Moreover, the converter exhibits the maximum$I_{\mathrm{OUT}}$s of 21 mA and 4 mA, respectively.

This paper presents a 4-GHz ring-oscillator-based digital sub-sampling phase-locked loop (SSPLL) with an energy-efficient dual-domain phase detector (DDPD). The performance of the digital SSPLL is limited by the quantization noise (Q-noise) of the phase detector (PD), and it requires an analog-to-digital-converter (ADC) and optimally spaced voltage comparators (OSVCs) with a large power and area overhead to reduce the Q-noise. The proposed DDPD efficiently detects a phase error in both the voltage- and time-domains, thereby suppressing the Q-noise while minimizing additional cost. It requires only one comparator in the power-hungry digitally-controlled oscillator (DCO) clock path unlike ADC and OSVCs. Consequently, it achieves a high performance while consuming a small amount of power similar to that of a conventional bang-bang phase detector (BBPD). The proposed SSPLL was implemented in a 28-nm CMOS technology. It consumes 5.35 mW at 4 GHz and occupies an area of 0.014 mm2. The integrated rms jitter is reduced by 25.7% using the proposed DDPD, whereas the overall power dissipation is similar to that of a conventional BBPD-based PLL. The jitter-power FoM1of the prototype SSPLL is −235.9 dB, and the FoM2is −250.9 dB.

This study presents a wireline pulse amplitude modulation-4 (PAM-4) receiver using the least significant bit (LSB) decoding method that uses the offset of comparators. The proposed LSB decoding method can generate the same output as that of a conventional comparator by effectively adding the desired offset voltage to only one of the differential PAM-4 signals. Because the proposed decoding method replaces a 4-input comparator with a 2-input comparator, it can improve the bit error rate (BER) performance of the LSB by as much as the most significant bit (MSB). The predetermined offset is useful not only for LSB decoding but also for the direct decision feedback equalizer (DFE) operation. The differential amplitude and common-mode voltage (VCM) of the PAM-4 signal vary owing to the direct DFE tap coefficient. The modified comparator can generate an appropriate offset voltage without an adaptation loop or a VCM compensator although the PAM-4 signals are changed depending on the DFE tap coefficient. A prototype is fabricated using 28-nm CMOS technology and tested using a 10.29 dB channel attenuation at 10 GHz. The maximum data rate is 40 Gb/s, and the power efficiency and area of the proposed architecture are 1.58 pJ/bit and 0.039 mm2, respectively.

In this paper, an all-digital delay-locked loop (ADDLL) with an adaptive phase rotator (PR) is proposed to meet the wide operating range in the LPDDR5 controllers. The conventional lattice-delay-unit (LDU)-based delay line is replaced by the PR-based digitally controlled delay line (DCDL) to achieve a wide operating range with a low jitter accumulation and low power dissipation. For the proper operation of the PR-based DCDL with high linearity, the current strength of the PR should be set to the optimum value for each operating frequency. The proposed ADDLL adaptively controls the current strength of the PR by detecting the output swing for each frequency. The proposed ADDLL is fabricated in a 28-nm CMOS technology occupying an active area of 0.0043 mm2. It operates from 266 MHz to 3750 MHz for the LPDDR5 interfaces. The measured jitterrmsis 2.06 ps, and the jitter$_{pk-pk}$ is 13.2 ps at 3750 MHz. The proposed ADDLL consumes 4.2 mW at 3750 MHz.

The required data rate of wireline communications has increased; however, channel attenuation limits the data bandwidth. Bit-efficient signaling is an effective and efficient solution because more data can be transmitted at the same Nyquist frequency. Several methods for increasing bit efficiency, such as multi-wire signaling, multi-level signaling, and symbol correlation schemes, have been proposed. Each scheme can generate additional codes by encoding the data. Additional codes can be used to transmit more data or to embed data transitions. In this study, the aforementioned schemes are analyzed, and a method is developed to combine them, maximize the bit efficiency, and ensure the data transition density. For the prototype transceiver, a 4-wire PAM-3 (4W3P) signaling scheme was adopted. The 4W3P signaling scheme can increase the bit efficiency to 200% while maintaining the DC-balanced characteristics. Transceiver building blocks, such as the TX driver, feed-forward equalizer, and analog front-end, were optimized for the proposed signaling scheme. The prototype transceiver was fabricated using 28 nm CMOS technology, occupying 0.012 mm2. The RX was measured using the TX and achieved a BER less than$10^{-12}$at 40 Gb/s over the four wires, with a total transceiver energy efficiency of 1.52 pJ/bit.

This paper proposes a hybrid DC-DC converter with a new power switch structure and its operating principles. Its main application is a power management IC that supplies compact mobile devices with a low-profile chip inductor, whose DC resistance is relatively high. In step-down mode, DC current flowing through the inductor is reduced by introducing a flying capacitor that assists load current at a certain phase. In step-up mode, average inductor current is smaller than the load current because of power-input power-output equation. A three-phase mode is also added to fill output voltage gap between step-up and step-down modes. By reducing inductor conduction loss, this work shows better power conversion efficiency than a conventional buck converter at heavy load. Using 180 nm general purpose process, the proposed converter takes 2.5 V input and supplies output in between 1.4 V and 5 V. Load current ranges in between 0.3 A and 1.5 A with peak power conversion efficiency of 92.87%.

This paper presents an adaptive dropout voltage regulator based on a constant on-time buck converter that improves the light load efficiency. By regulating the gate voltage of the pass transistor of the low dropout regulator (LDO), the dropout voltage is automatically minimized depending on the load current, increasing the end-to-end power conversion efficiency at the light load condition by 11.3%. The proposed direct-charging scheme and simple undershoot detector reduce the droop and improve the efficiency of the LDO. The reference pre-compensation technique is proposed to improve the ripple performance by compensating the reference voltage based on the on-time pulses. The proposed voltage regulator was fabricated by a 0.18-wm CMOS process and occupies 0.2874 mm2.

Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2 GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty cycle, to mitigate the offset of the BBDCD, an average codes method is used. The operating frequency is determined according to capacitance in the BBDCD for a wide frequency. A duty cycle adjuster (DCA) based on a 2-input NAND gate makes a clock with pulse width from the rising edge of the input clock to the falling edge of the digitally controlled delay line (DCDL) output. The IC is designed in CMOS 28nm process. The maximum duty cycle error of the DCC is 1.5 % at 3.2 GHz. The DCC consumes 1.92 mW at the maximum input frequency. The peak-to-peak jitter of the output clock is 12 ps.

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/f noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency ( fch) same as the sampling frequency ( fs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/ √{Hz} input-referred noise density, 1.9 μV offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With -110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique.

This article presents an receiver (RX) only equalization (ROE) technique that eliminates feed-forward equalization (FFE) in transmitter (TX) and bandwidth improved output driver without increment of power consumption. With a help of the proposed design technique, the power consumption, circuit complexity, and design cost are improved. The proposed RX with one-tap finite-impulse response (FIR) and second-tap IIR decision feedback equalizer (DFE) removes the FFE equalization in TX by moving the sampling point of main cursor in the received data. A simpler TX architecture with nMOS only output driver (NOD) owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) operation. The proposed transceiver was fabricated in a 65-nm CMOS technology. The RX achieves bit error rate (BER) less than 10^{-12} over a 22-dB channel loss at 32 Gb/s with 0.62-pJ/bit energy efficiency, and the TX with NOD has 0.77- and 0.40-pJ/bit energy efficiency at 32 Gb/s in differential mode and single-ended mode, respectively. The occupied area of TX and RX is 0.002 and 0.024 mm2, respectively.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

An energy efficient State-of-Charge (SOC) indication algorithm and integrated system for small IoT batteries are introduced in this paper. The system is implemented in a 180-nm CMOS technology. Based on a key finding that small Li-ion batteries exhibit a linear dependence between battery voltage and load current, we propose an instantaneous linear extrapolation (ILE) algorithm and circuit allowing on-demand estimation of SOC. Power consumption is 42nW and maximum SOC indication error is 1.7%.

This paper presents a Braid clock signaling scheme with 100% data payload and spread transition scheme. The Braid clock signaling has NRZ signaling margin without any dummy clock bits. Also, this paper describes spread transition schemes for low EMI radiation. The effective data bandwidth is increased by 11.1% with the 500% highly embedded transitions. With a same RX voltage margin, the required power for the termination is 5.4 times smaller than the multi-level signaling.

This paper presents a new energy-efficient ring oscillator collapse-based comparator, which is called edge-pursuit comparator (EPC) and demonstrated it in a 15-bit SAR ADC. The comparator automatically adjusts the performance according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. The employed SAR ADC supplements a 10-bit differential main CDAC with a 5-bit common-mode CDAC which uses common to differential gain tuning to improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40nm CMOS shows 74.12 dB SNDR and 173.4 dB FOMs. The comparator consumes 104 nW with the full ADC consuming 1.17 μW.

As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.

A 10 Gbits/s/pin graphics DRAM interface is developed in 65-nm CMOS technology. Several design techniques are proposed for high-speed operation in a noisy environment. A fast precharging data sampler guarantees high-speed sampling without the need for a decision feedback equalizer. In order to increase the data sampling margin, the PLL bandwidth is optimized depending on the system noises, which reduces the clock jitter by up to 55.1%. The crosstalk-induced jitter (CIJ) reduction technique suppresses the DQs jitter by employing the suggested training sequence for the GDDR5 interface. Pre- and de-emphasis are merged in one auxiliary driver. This chip operates at 10 Gbits/s/pin and exhibits a data eye opening of 0.78 UI with the CIJ reduction technique. The power consumptions of the TX and RX are 8.28 and 5.5 pJ/b/channel, respectively.

An add-on type real-time jitter tolerance enhancer (JTE) is presented in this paper. The proposed JTE can improve high-frequency jitter tolerance (JTOL) by using a real-time phase alignment scheme. A mathematical analysis for an advanced bit error rate (BER) prediction method is also introduced. The proposed circuit is applicable to various types of receivers, such as referenceless receivers, receivers with a reference clock source, and source-synchronous receivers. The referenceless receiver with the proposed JTE achieved an out-of-band JTOL of 0.71 UIppat 100 MHz with-12BER. This is 196% higher than a conventional receiver without the JTE. The source-synchronous receiver with the proposed JTE achieved 0.92 UIpp at 300 MHz with-12BER. Total core areas of the receiver and JTE are 0.19 and 0.07 mm2in a 0.13-μm CMOS process, respectively. The power consumption of the receiver is 38 mW at 5.4 Gbit/s, and the JTE dissipates 22 mW.

A 4×5-Gb/s reference-less receiver is proposed in a 0.13-μm CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12-μs locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 psrms, and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.

This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog converter (RASD). By applying the input folding technique in the input stage and utilizing the flash-assisted TI-SAR ADC with the proposed RASD, the static power dissipation is reduced by 69%. ON-chip and OFF-chip calibration techniques are used to compensate the interchannel error sources. The prototype was fabricated in a 65-nm CMOS process technology. The peak integral nonlinearity and differential nonlinearity are measured as 0.52 and 0.51 LSB, respectively. At 2.5 GS/s, a signal-to-noise and distortion ratio (SNDR) of 18.6/31.9 dB and a spurious-free dynamic range (SFDR) of 23.7/42.1 dBc are measured before and after the calibration at the Nyquist input frequency with 1 Vpp-diff input signal, and the figure of merit is 0.27 pJ/conversion-step. This chip consumes 22 mW at 1.2-V supply and occupies 0.27-mm2 area.

This paper describes a time-limited power distribution control (TPDC) technique that can be used for single-inductor multiple-output (SIMO) DC-DC converter with many unbalanced loads. Furthermore, the true all-comparator control technique that raises no stability or complexity issues is proposed. This all-comparator technique for SIMO converters is realized only with a single shared hysteresis comparator at a constant switching frequency of 800 kHz. The maximum efficiency reaches 92%. The fabricated chip with 8-channel outputs occupies 2.4×2.1 mm2in a 0.35-um CMOS process.

This paper presents a boost converter with the maximum power point tracking (MPPT) technique for thermoelectric energy harvesting (EH) applications. The technique realizes variation tolerance by adjusting the switching frequency fSWof the converter. A finely controlled zero-current switching (ZCS) scheme together with the accurate MPPT technique enhances the overall efficiency (η) of the converter because of an optimal turn-on time generated by a one-shot pulse generator that is proposed. Moreover, the ZCS technique can deal with low and high temperature differences applied to the thermoelectric generator. Experimentally, the converter implemented in a 0.35 um BCDMOS process had a peak of 72% at the input voltage VINof 500mV while supplying a 5.62V output.

Cameras and image sensors have recently been installed in many portable devices. An image processor and a transceiver are also adopted in multimedia system-on-a-chip to handle the data from the image sensor. A wide input range and flexible data bandwidth are needed for the serial link receiver to deal with various sensor specifications. This paper presents an 11.2-Gb/s low-voltage differential signaling (LVDS) receiver for various portable devices that employ a LVDS system for data transmission between an image sensor and a processor. The designed LVDS receiver has 16 data channels and four clock channels. All the channels are selectively turned on or off, depending on the application. The proposed comparator used for the input driver of the receiver has a rail-to-rail input range and 60 mV of minimum input swing level. The clock dividing ratio and the data de-serializing factor of the proposed receiver are also programmable to deal with various color depths of image sensors. The designed LVDS receiver is fabricated in a 0.13-μm CMOS process, occupying 4-4 mm, with a 7.24-mm2core. Power consumption is 77.38 mW, when every channel is turned on.

In this paper, delay-locked loops (DLLs) used in dynamic random access memory (DRAM) are analyzed. DLLs can be categorized into digital- or analog-based topologies. This analysis starts with an explanation of technology trends regarding DLL for DRAM in the early 1990s and describes important DLL specifications and design approaches necessary for DLL use in DRAM: lock time, lock range, lock cycles, tDQSCK (DQS rising edge output access time from the rising edge of CK), and wake-up time from power down modes. DLLs have been widely used since 2000 to satisfy high operating speed requirements inherent in DRAMs. Finally, referring to studies published from 2000 to 2011, trends regarding power consumption, jitter, relationship between power and jitter, lock range, lock cycles, and wake-up time from power down are analyzed.

This paper presents a regulated charge pump (CP) with an integrated optimum power point tracking (OPPT) algorithm designed for indoor solar energy harvesting. The proposed OPPT circuit does not require a current sensor that consumes power proportionally to the load. The solar cell voltage is regulated at the optimum power point; the CP output is regulated according to the target voltage. The controller of the OPPT circuit and CP dissipates only 450nW, so the proposed technique is appropriate for indoor solar energy harvesting applications under dim lighting conditions.

A 7.5Gb/s referenceless transceiver for the ultra-high definition television is designed in a 0.13μm CMOS process. By applying the dynamic pre-emphasis calibration and the bandwidth scanning clock generators, measured eye opening and jitter of the clock are enhanced by 39.6% and 40%, respectively. Also the data-width comparison based adaptive equalizer with self-adjusting reference voltage is proposed.

This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of 0.5× to 8× of the reference clock, according to the workload of the EISC processor. The proposed analog self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in a 0.18-μm CMOS process occupies an active area of 0.27 mm2and consumes 15.56 mA.

A smart temperature sensor in 65-nm CMOS, utilizing CMOS ring oscillators, consumes 1.09 nJ at a conversion rate of 366 kS/s. This is achieved by the direct temperature-to-digital conversion method implemented in the frequency-to-digital converter. The algorithm utilized in the fine code generator makes it possible to increase the resolution of the sensor efficiently. Compared to previous work, this brief shows lower VDD operation. After one point calibration, the chip-to-chip spread is +2.7 ~ -2.9°C over the temperature range of -40°C to 110°C.

Coarse grained arrays (CGAs) with run-time reconfigurability play an important role in accelerating reconfigurable computing applications. It is challenging to design on-chip communication networks (OCNs) for such CGAs with dynamic run-time reconfigurability whilst satisfying the tight budgets of power and area for an embedded system. This paper presents a silicon-proven design of a 64-PE circuit-switched OCN fabric with a dynamic path-setup scheme capable of supporting an embedded coarse-grained processor array. A proof-of-concept test chip fabricated in a 0.13 μm CMOS process occupies a silicon area of 23 mm2and consumes a peak power of 200 mW @ 128 MHz and 1.2 Vcc, at room temperature. The OCN overhead consumes 9.4% of the area and 18% of the power of the total chip. Experimental results and analysis show that the proposed OCN fabric with its dynamic path-setup is suitable for use in an embedded CGA supporting fast run-time reconfigurability.

This paper presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in multiprocessor system-on-chip applications. The proposed network employs a pipelined circuit-switching approach combined with a dynamic path-setup scheme under a multistage network topology. The dynamic path-setup scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks. A 0.13-μ m CMOS test-chip validates the feasibility and efficiency of the proposed design. Experimental results show that the proposed on-chip network achieves 1.9× to 8.2× reduction of silicon overhead compared to other design approaches.

We propose a novel modulation profile for a spread spectrum clock generator (SSCG). The proposed piecewise linear (PWL) modulation profile significantly reduces electromagnetic interference with a simple implementation. Two SSCGs with two- and three-slope-PWL modulation profiles are used. Both SSCGs consist of the proposed spread spectrum control profile generator and a phase-locked loop that includes a high-resolution fractional divider to reduce quantization noise from a delta-sigma modulator. The SSCG with the two-slope-PWL modulation profile was fabricated in a 0.18 μm 1P4M CMOS technology. The measured peak power reduction level of the two-slope-PWL modulation profile is 14.2 dB with 5000 ppm down spreading at 1.5 GHz. The SSCG occupies an active area of 0.49 mm2and consumes 40 mW of power at 1.5 GHz. The SSCG with the three-slope-PWL modulation profile was fabricated in a 0.13 μm 1P6M CMOS technology. The measured peak power reduction level of the three-slope-PWL modulation profile is 10.3 and 10.52 dB with 5000 ppm down spreading at 162 and 270 MHz, respectively. The SSCG occupies an active area of 0.096 mm2and dissipates 1 mW of power at 270 MHz.

A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70 pspp, respectively, with a multiplication factor of 1024.

An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10-12at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm2using 0.13μm CMOS process.

A current source with a small current error has been proposed to maintain the bandwidth of the system without an increase in power consumption for a margin. It minimizes the current error under process, supply voltage, and temperature (PVT) variations. Because the on-resistance of the nMOS array is self-calibrated digitally by an on-chip digital PVT detector, a current error of only ±2% is achieved. The current source has been implemented in an 80-nm CMOS process, occupies 0.018 mm2and consumes 94.9 μW at a supply voltage of 1.0 V.

This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm2. The measured duty-cycle error for the 50% duty-rate is below 1% (or 10 pS) within 320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

It is a challenging task in a network-on-chip to design an on-chip switch/router to dynamically support (hard) guaranteed throughput under very tight on-chip constraints of power, timing, area, and time-to-market. This paper presents the design and implementation of a novel pipeline circuit-switched switch to support guaranteed throughput. The proposed circuit-switched switch, based on a backtracking probing path setup, operates with a source-synchronous wave-pipeline approach. The switch can support a dead- and live-lock free dynamic path-setup scheme and can achieve high bandwidth and high area and energy efficiency. A silicon-proven prototype of a 16-bit-data 5-bidirectional-port switch in a four-metal-layer 0.18-μ m CMOS standard-cell technology can yield an aggregate data bandwidth of up to 73.84 Gb/s, while occupying only a modest area of 0.0315 mm2. The synthesizable implementation of the proposed switch also results in a cost-effective design, fast development time, and portability.

This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The RMS jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2in a 0.25-μm 1P5M CMOS technology.

A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and-distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 × 0.8 mm2of active area.

A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed for low power and high frequency operation. This DLL utilizes an OR-AND DCC for wide duty cycle correction capability. The proposed DLL for DDR3 SDRAM is fabricated by a 54nm DRAM process technology. Experimental results show that ±10% duty error of external clock can be corrected in less than 400 cycles locking time with 1.0GHz operation frequency at 1.35V.

In this paper, we present a novel architecture of a block interleaver in MB-OFDM systems based on Mixed Radix System (MRS). We prove mathematically that the proposed architecture can support bit permutations in the interleaving process. The hierarchical property of our proposed MRS-based design methodology allows the proposed architecture to support all the required data rates in the MB-OFDM systems with simple modular design. Furthermore, the same design to be used for the interleaver can also be used for the operation of de-interleaving, which reduces the implementation complexity significantly. The latency of our architecture is as low as 6 MB-OFDM symbols. In addition, when comparing our proposed architecture with the conventional approach, we are able to reduce the implementation complexity by 85.5%, 69.4%, and 40.3% for 80, 200, and 480 Mb/s data rates, respectively, while improving our operating maximum clock frequency by more than 3.3 times over the conventional design. We also show that the power consumption is reduced by 87.4%, 73.6%, and 39.8% for 80, 200, and 480 Mb/s, respectively.

This paper describes a new delay-locked loop (DLL)-based frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the frequency multiplication. The antiharmonic DLL-based frequency multiplier, implemented in a 0.18-μ.m CMOS process, occupies an active area of 0.043 mm2, and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.

An all-digital fast-lock synchronous multi-phase clock generator is presented. By using a time-to-digital converter for fast-lock operation and delay measurement, the proposed multi-phase clock generator generates four-phase clocks and synchronizes the reference clock with the output clock within 45 cycles. Furthermore, the clock generator uses a fine binary scheme and de-skewing circuit for fine delay measurement and compensation. The proposed clock generator was designed in a 0.18 mum CMOS technology. It operates over a wide frequency range from 400 MHz to 1.22 GHz and consumes 34 mW at 1.22 GHz.

A portable clock generator, which solves the duty ratio and jitter problems of the input clock, has been developed. In the proposed clock generator, the complementary delay line generates a series of multiphase clocks. The 0-to-1 transition detector finds the 2 pi phase delayed position among the multiphase clocks produced by the complementary delay line, and then, the select signal generator chooses the proper path to generate the delayed output clock. As a result, the proposed open-loop and full-digital architecture achieves a fast lock time of two clock cycles. Also, it is a simple, robust and portable IP and consumes only 17 mW at an input clock frequency of 1.6 GHz. In addition, a complementary delay line is implemented to achieve high phase resolution over a wide frequency range. The proposed clock generator is implemented in a 0.18-mum CMOS process and, occupies an active area of 170 mum times 120 mum. Also, it operates at various input frequencies ranging from 800 MHz to 1.6 GHz.

A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13 um CMOS technology occupies only 0.004 mm and operates at variable input frequencies ranging from 625 MHz to 1.2GHz.

A low-power slew-rate controlled output driver with open loop digital scheme, one-cycle lock time is presented. Proposed output driver maintains slew rate in the range of 2.1V/ns to 3.6V/ns in a one cycle after the enable clock is inserted. It is implemented in 0.18um CMOS process, and the control block consumes 13.7mW at 1Gbps.

It is critical to understand user requirements in Web site development. As a method of user requirements analysis for a self-help technical support Web site, focus group interviews can be a very efficient and effective approach both before the interface has been designed and after it has been in use for some time. This article shows how focus group interviews were used to develop a self-help technical support Web site for print quality troubleshooting. It also shows how focus group interviews led to improvements in the efficiency and effectiveness of the Web site. In addition, the article classifies the critical usability issues identified and shows how the feedback from focus group interviews is reflected in the Web site development. Finally, experimental results demonstrate that the use of focus group interviews significantly improved user performance and preference.

In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S/sup 2/L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-/spl mu/m CMOS technology and verified that S/sup 2/L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S/sup 2/L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S/sup 2/L is developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.

This paper presents S/sup 2/L, which exhibits low-power, high-speed with use of positive feedback circuits and dual Vt. Topology-dependent dual Vt approach suppresses leakage current while boosting the performance in VDSM technology. S/sup 2/L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. We present simulation results of NAND-NOR gate chains and 32-b adders to demonstrate the effectiveness of the S/sup 2/L compared to other techniques. Design automation for the proposed circuit architecture can be achieved easily due to cascading flexibility.

In this paper, we describe parallel dynamic logic (PDL) which exhibits high speed and no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 /spl mu/m CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power delay by 20-37%.

In this paper, we describe NMOS Energy Recovery Logic (NERL) which exhibits high throughput with low energy consumption due to efficient energy transfer and recovery using adiabatic and bootstrapping techniques. NERL shows full output voltage swing, insensitivity to output load capacitance, less dependency on power-clock frequency and complementary outputs for balanced capacitance load to power-clock. We have designed an 8-bit CLA and inverter chain using 0.6 /spl mu/m CMOS technology and verified that NERL saves energy over ECRL by 2 to 3 times.