Article T: integrated building blocks for parallel computing Share on Authors: G. M. Papadopoulos Lab for Comp. Sci., MIT 545 Technology Square, Cambridge, MA Lab for Comp. Sci., MIT 545 Technology Square, Cambridge, MAView Profile , G. A. Boughton Lab for Comp. Sci., MIT 545 Technology Square, Cambridge, MA Lab for Comp. Sci., MIT 545 Technology Square, Cambridge, MAView Profile , R. Greiner Motorola, Motorola, Inc., DW220, 2900 South Diablo Way, Tempe, AZ Motorola, Motorola, Inc., DW220, 2900 South Diablo Way, Tempe, AZView Profile , M. J. Beckerle Motorola, Motorola Cambridge Research Center, One Kendall Square, Bld 200, Cambridge, MA Motorola, Motorola Cambridge Research Center, One Kendall Square, Bld 200, Cambridge, MAView Profile Authors Info & Claims Supercomputing '93: Proceedings of the 1993 ACM/IEEE conference on SupercomputingDecember 1993 Pages 624–635https://doi.org/10.1145/169627.169811Online:01 December 1993Publication History 20citation170DownloadsMetricsTotal Citations20Total Downloads170Last 12 Months4Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The interconnection network is described for Monsoon, a parallel processing dataflow computer. This network provides reliable, high bandwidth, low latency communication between the nodes of Monsoon. The major components of this network are two gate arrays: PaRC and the data link chip (DLC). PaRC (packet switched routing chip) is a CMOS gate array that implements a 4*4 packet routing switch that provides a high raw bandwidth (800 Mb/s) to each port. PaRC is designed so that much of this bandwidth can be utilized. The DLC is a high speed ECL gate array that reliably transfers data between boards.>

A variety of proposed architectures for data flow computers have been advanced. Evaluation of the practical potential of these proposals is being studied through analysis and simulation, but these techniques cannot be used to study a machine design in sufficient detail to make accurate predictions of performance. As a basis for extrapolating cost/performance of these architectures, and for developing a methodology for data flow program preparation, the construction of prototype machines is needed. In this paper we present our plan for realizing experimental data flow machines as packet communication systems using two types of hardware elements: a microprogrammed processing element with provision for packet transmission and reception; and a router unit used to build networks to support packet communication among processing elements.