Road accidents are a major cause of death in urban areas. Cooperative Intelligent Transport Systems may mitigate or prevent road accidents by providing drivers with relevant and timely warnings, thanks to V2X communications. However, this requires fast detection of dangers, performed at the edge, to minimize transmission latencies and ensure the timeliness of the warnings. The PMDI project extends the STEP platform for intelligent mobility to support real-time operations and ETSI message generation, and provides integration with mobile and embedded systems.

The advancement of the agricultural economic sector, which is a labour-intensive one, can benefit from robot-based systems, able to identify objects and perform complex processes in cooperation with human actors. From the technical, organizational, and job management viewpoint, cooperation in agriculture can also help facing challenges related to sustainability and climate change, and connected to aspects of the market such as global competition, labour shortages, and fluctuating costs of materials (e.g., fuel and fertilisers). Agricultural robots (agrobots) hold great promise in addressing the aforementioned challenges. Starting from ideas at the basis of our project at POLIMI on fruit farming, this paper presents a context study, and a knowledgebased approach to model smart agricultural environments, where farms use sensors and agrobots, and cooperate via Digital Twins towards the execution of complex tasks. We discuss how Artificial Intelligence (AI) can enhance the process of training humans and agrobots in cooperative tasks.

The development of a contact-less monitoring system detecting water flow in the household and identifying the objects utilizing it, can provide support for Human Activities Recognition (HAR) and for Activities of Daily Living (ADL). This makes it particularly valuable in the context of Ambient Assisted Living (AAL). This study presents the results of an approach based on analyzing the spectrum of sounds captured in the environment. Two non-invasive solutions are examined, both utilizing a platform with a microphone placed in the environment to detect changes in sound caused by water flow noise. One method is based on spectrum analysis; the other on spectrogram analysis. We present the experiments conducted to test the two approaches in different environments. The two approaches differ in computational cost and are suitable for environments with multiple water sources, requiring no direct contact with plumbing. This makes them particularly suitable for applications related to the use of the bathroom. In particular, the spectrogram approach achieves an accuracy above 90%.

The significant growth of the average age of the world population requires effective solutions to meet the unsustainable number of requests for hospitalization. For this reason, the scientific community is seeking new paradigms of care that provide compensatory interventions to the first signs of warning that can be detected in the behavior of the individuals. At this aim, this work proposes a method to detect the Activities of Daily Living carried out by a subject monitored at home through unobtrusive environmental sensors. The Activity Recognition system is composed of an unsupervised segmentation layer which splits the collected sensors activation data in time periods and a semantic layer that exploits a knowledge-based approach to provide the most probable activity label for each period. The system is enriched with a further layer to adapt the base knowledge according to the information directly provided by the resident.

Functional diagnosis for complex systems can be a very time-consuming and expensive task, trying to identify the source of an observed misbehavior. We propose an automatic incremental diagnostic methodology and CAD flow, based on data mining (DM). It is a model-based approach that incrementally determines the tests to be executed to isolate the faulty component, aiming at minimizing the total number of executed tests, without compromising 100% diagnostic accuracy. The DM engine allows for shorter test sequences with respect to other reasoning-based solutions (e.g., Bayesian belief networks), not requiring complex pre and post-conditions management. Experimental results on a large set of synthetic examples and on three industrial boards substantiate the quality of the proposed approach.

Gestural interaction leveraging the expressiveness of the human hand, either in touch or in air gestures has been a subject of much research. In this work, a user study focusing mainly on static hand poses has been conducted on a heterogeneous group of participants covering different aspects of this interaction method: role of the participants in the creation of the hand poses, context-free pose-action mapping, learnability and memory issues, and physical comfort. Results of the study are discussed.

Thanks to the large diffusion of small wearable devices there are several systems designed for indoor localization. Among the pro- posed solutions, RF-based systems have been deeply investigated due to their flexibility and limited costs. When these systems are employed as assistive tools, they s

iAF2D (incremental Automatic Functional Fault Detective) is a methodology for the identification of the faulty component in a complex system using data collected from a test session. It is an incremental approach based on a Bayesian Belief Network, where the model of the system under analysis is extracted from a faulty signature description. iAF2D reduces time, cost and efforts during the diagnostic phase by implementing a step-by-step selection of the tests to be executed from the set of available tests. This paper focuses on the evolution of the BBN nodes probabilities, to define a stop criterion to interrupt the diagnosis process when additional test outcomes would not provide further useful information for identifying the faulty candidate. Methodology validation is performed on a set of experimental results.

Fault diagnosis is the task of identifying a faulty component in a complex system using data collecting from a test section. Diagnostic resolution, that is the ability to discriminate a faulty component in a set of possible candidates, is a property that the system model must expose to provide accuracy and robustness in the diagnosis. Such a property depends on the selection of an appropriate test set capable to provide a unique interpretation of the test outcomes. In this paper a quantitative metric for the evaluation of diagnostic resolution of a test set is proposed, together with an algorithm for the minimal extension of a given test set in order to provide a complete discrimination of failures affecting a system, to be used as a support for analysts during the definition of a testing framework.

Convolutional coding is usually exploited to protect data transmitted over channels, where they are more susceptible to errors. However in recent years, an increasing interest has been drawn to the problem of radiation-induced temporary faults, also called soft errors, which corrupt memory content even during the normal functioning of a system. In this paper, a mitigation technique for the protection of critical data in electronic devices from transient errors that manifest themselves as bit-flips in memory is proposed. In order to cope with this problem we take advantage of convolutional codes and we introduce two architectures to protect memory content with little area and performance overheads. A coding-decoding scheme implemented using sequential logic. The encoding is performed as in classical convolutional encoding, processing the input stream with a shift-register based architecture. The decoder, however, differs from classical decoding schemes in terms of complexity.

The growing complexity of digital systems and the increase of available silicon area are drawing attention on the problem of how to fill the productivity gap. Many initiatives are possible, ranging from raising the abstraction level, to mixing solutions targeted to the hardware and software domains. This paper proposes a design approach that raises the abstraction level, maintaining a tight link with the hardware and software domains, through the use of highly parametric, technology independent and easily modifiable hardware and software cores. Key features of the methodology are the exploration of the solution space, carried out to identify not only a hardware/software partitioning but also a finer tuning of alternative implementations in both the domains, and the back-annotations that enrich the description model and allow for faster design-loops and for a closer control on the underlying architecture. As a case study the paper describes the implementation of one physical layer of the 802.16-2004 protocol (WiMax) evaluating different hardware/software solutions.

Continuous advances in silicon technology enable the development of complex system-on-chip as cooperation among digital signal processors (DPSs), general purpose processors (GPPs), and specific hardware components. The impact of this choice is not only limited to the target architecture, but also encompasses the overall system specification. It is thus crucial to manage such a complexity using high-level specification languages and a tool chain supporting the designer throughout a set of strategic decisions, such as the identification of a set of possible target architectures, the verification of the correctness of the specification, and the partitioning of the specification onto a set of computational resources. This paper addresses this type of problem by proposing a design flow supporting the system-level design of heterogeneous multiprocessor system-on-chip (MP-SoC), by extracting information from the system description (e.g., SystemC) - statically and in a fast manner - and by providing a set of quantitative measures correlating the type of executor, the functionality, and a timing estimation. Partitioning and architecture selection are built on top of this data and the final analysis of the selected hardware-software solution over the identified candidates is finally submitted to a timing verification via simulation. Note that the possibility of actually performing a comprehensive design space exploration, in general, is tightly influenced by the interaction between partitioning/architecture-selection and timing simulation in the design flow; for this reason, the description of this aspect is particularly emphasized in the presentation of the methodology. To show the applicability of the proposed methodology, two relevant case studies are described in the paper.

We present a very first step toward the implementation of the XCS classifier system on field programmable gate arrays. We introduce a version of the XCS classifier system completely based on integer arithmetic instead of the usual floating point one. We test the integer based XCS, that we name XCS/sub i/, on the typical Boolean functions used in literature. The results we present show that, notwithstanding the dramatic reduction of available precision, XCS/sub i/ can perform rather well reaching optimality in all problems though in most cases it converges more slowly than the classical floating point version.

The design of reliable circuits has received a lot of attention in the past, leading to the definition of several design techniques introducing fault detection and fault tolerance properties in systems for critical applications/environments. Such design methodologies tackled the problem at different abstraction levels, from switch-level to logic, RT level, and more recently to system level. The aim of this paper is to introduce a novel system-level technique based on the redefinition of the operator functionality in the system specification. This technique provides reliability properties to the system data path, transparently with respect to the designer. Feasibility, fault coverage, performance degradation and overheads are investigated on a FIR circuit.

This paper presents a parametric area estimation methodology at SystemC level for FPGA-based designs. The approach is conceived to reduce the effort to adapt the area estimators to the evolutions of the EDA design environments. It consists in identifying the subset of measures that can be derived form the system level description and that are also relevant at VHDL-RT level. Estimators' parameters are then automatically derived from a set of benchmarks.

This paper presents a methodology and a set of models supporting energy-driven source-to-source transformations. The most promising code transformation techniques have been isolated and studied leading to accurate analytical and/or statistical models. Experimental results, obtained for some common embedded-system processors over a set of typical benchmarks, are presented, showing the viability of the proposed approach as a support tool for embedded software design.

The design of very small databases for smart cards and for portable embedded systems is deeply constrained by the peculiar features of the physical medium. We propose a joint approach to the logical and physical database design phases and evaluate several data structures with respect to the performance, power consumption, and endurance parameters of read/program operations on the Flash-EEPROM storage medium.

The paper presents a novel strategy aimed at modeling instruction energy consumption of 32-bit microprocessors. Different from former approaches, the proposed instruction-level power model is founded on a functional decomposition of the activities accomplished by a generic microprocessor. The proposed model has significant generalization capabilities. It allows estimation of the power figures of the entire instruction-set starting from the analysis of a subset, as well as to power characterize new processors by using the model obtained by considering other microprocessors. The model is formally presented and justified and its actual application over five commercial microprocessors is included. This static characterization is the basic information for system-level power modeling of hardware/software architectures.

The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter-instruction effects. Such effects depend on the processor state and the pipeline behavior, and are related to the dynamic execution of assembly code. The paper proposes a mathematical model of the delays deriving from instruction dependencies and gives a statistical characterization of such timing overheads. The model has been validated on a commercial architecture, the Intel486, by means of timing analysis of a set of benchmarks, obtaining an error within 5%. This model can be seamlessly integrated with a static energy consumption model in order to obtain precise software power and energy estimations.

The paper presents a novel strategy aimed at modeling the instruction energy consumption of 32-bits microprocessors. The proposed instruction-level pow er model is founded on afunctional decomposition of the activities accomplished by a generic microprocessor and exhibits significant generalization capabilities. It allo ws estimation of the pow er figures of the en tire instruction-set starting from the analysis of a subset, as w ell as to po w er characterize new processors using the model obtained by considering other microprocessors.

This paper presents a complete methodology to design a totally self-checking (TSC) sequential system based on the generic architecture of finite-state machine and data path (FSMD), such as the one deriving from VHDL specifications. The control part of the system is designed to be self-checking by adopting a state assignment providing a constant Hamming distance between each pair of binary codes. The design of the data path is based on both classical methodologies (e.g., parity, Berger code) and ad hoc strategies (e.g., multiplexer cycle) suited for the specific circuit structure. Self-checking properties and costs are evaluated on a set of benchmark FSM's and on a number of VHDL circuits.

Fast evaluation of functional and timing properties is becoming a key factor to enable cost-effective exploration of mixed hw/sw design alternatives for embedded applications. The goal of this paper is to present a modeling strategy to specify functionality and timing properties of uncommitted mixed hw/sw systems. In addition, the paper proposes a simulation algorithm able to perform fast high-level simulation of the system by taking into account the initial hw vs. sw allocation of system modules. The related CAD simulation environment allows the designer to access profiling information which can be useful to remodel the system to meet the functional/timing goals as well as to drive the following hw vs sw partioning activity. Experimental data obtained by reengineering an industrial design are also included in the paper.

The design of self-checking circuits through output encoding finds a bottleneck in the realization of the network so that each fault produces only errors detectable by the adopted code. An analysis of an expected TSC network is proposed, based on the application of the weighted observability approach. The aim is the verification of the SC property of the encoded circuit (TSC fault simulation) and identification of critical areas for a consequent manipulation to achieve a complete fault coverage.

The design of an embedded system is a process where the tuning of the architecture should take into account both the functionality and the timing performance while considering the heterogeneity of the hw and sw components. The goal of this paper is to present the new model developed during the SEED Esprit project, to estimate the software and hardware characteristics for cosimulation and profiling within the TOSCA codesign framework. The impact on the design space exploration of such an high-level cosimulation strategy has been tested by considering as a benchmark the reengineering of an industrial device.

A new methodology for designing Totally Self-Checking combinational circuits through the encoding of the primary outputs with the parity code is presented. The parity code requires that each fault modifies an odd number of outputs for providing its detection, that is, each fault has to be oddly observable. The proposed methodology for fulfilling such a constraint consists of a post-synthesis modification of fault observability through either the introduction of an auxiliary output for the examined network node or the replication of the investigated node. A cost evaluation function allows us to select the most convenient solution in terms of overhead and the final 100% TSC circuit.

The steadily growing demand of fast turnaround time will shift system tuning from physical prototyping to virtual prototyping. The paper proposes a novel approach for mixed HW-SW implementation of embedded systems, allowing high-level simulation of the overall architecture as well as a deeper analysis of timing performance by exploiting commercial VHDL CAD tools. At the higher level, functional debugging and tradeoff analysis is performed on an OCCAM-based system-level model and at the lower level a VHDL-based description for both the HW and SW is built for fine grain verification of the system. The paper introduces the two levels of simulation, showing their impact in terms of design flow management and design time.

The paper presents an innovative evaluation function for circuits with on-line detecting properties, which considers other aspects beyond area overhead. In particular, this function takes into account the probability of detecting a fault, once it occurs, with respect to the network structure and the application of input configurations. Different implementations of the same device designed to have TSC properties are compared with respect to this innovative evaluation function.

VLSI circuit implementation using transmission gates allows improvement of both circuit density and performances, without increasing power dissipation. Moreover, in self-checking structures, it allows detection of a larger class of faults than fully CMOS structures. This is true in particular for 1-out-of-3 codes, for which no gate level implementation of a self-checking checker (with respect to stuck-at faults) has been found yet. In this paper a self-checking checker for 1-out-of-3 codes obtained through a formalized synthesis procedure is presented and compared with other checkers to verify its performances.

This brief presents a novel high-performance architecture for implementation of custom digital feed forward neural networks, without on-line learning capabilities. The proposed methodology covers the entire design flow of a neural application, by addressing the internal neuron's structure, the system level organization of the processing elements, the mapping of the abstract neural topology (obtained through simulation) onto the given digital system and eventually the actual synthesis. Experimental results as well as a brief description of the software environment supporting the proposed methodology are also included.