Streaming applications are often described using dataflow actor models with a fixed network structure, allowing for static analysis and efficient hardware implementation. However, this fixed structure hinders scalability and design space exploration. This article investigates a representative dataflow toolchain, the StreamBlock compiler for the CAL actor language, along with its Actor Machine (AM) Intermediate Representation (IR), identifying limitations in handling parametric application specifications. To address these limitations, we extend CAL to support parametric actor and network specifications allowing a single description to capture multiple problem sizes. We demonstrate these extensions with a parametric QR Decomposition application and benchmarks from the Savina Actor Benchmark Suite. When compiling actor specifications to software or hardware, the AM IR is used for optimisation purposes. The AM defines a controller specifying how actors should behave at runtime. We show that as the complexity of the actor increases, the AM model scales poorly, leading to compilation failing. In this work, we improve the AM model enabling the compilation of actors up to six times larger than previously possible. For specifications targeting FPGAs, we offer an alternative to the AM designed to take better advantage of available hardware parallelism. Our results show that this controller scales better with the size of the actor compared to the AM controller, reducing latency significantly for a slight increase in resources used. These contributions extend CAL’s applicability, making it easier to specify and scale a broader range of streaming applications.

Stream processing applications are naturally described as dataflow programs. Dataflow programs modelled as actor networks are well suited to describe concurrent and computationally intensive problems. Realistic dataflow programs are typically characterized by highly dynamic behaviour, limiting the applicability of static analysis techniques. In this work we explore using dynamic analyses of dataflow programs by making use of causation traces; graphs which capture instances of the program's execution. We outline how they can be used to inform pipelining and architectural decisions and conclude by delineating how this research can be expanded upon using multiple traces and doing more types of analyses.

Custom architectures are often adopted as more efficient alternatives to general purpose processors in terms of performance and power. However, the design of such architectures requires experts both in hardware and the application domain. In this paper we propose a method for speeding up the design space exploration. Our method, based on Pareto points, identifies sets of solutions in terms of scalar units and vector units of certain length, fulfilling the throughput constraints for each application in a given set. Architectures can then be selected by combining these solutions, as starting points for a more thorough, model-based evaluation.

We are interested in mapping hard real-time applications on distributed heterogeneous architectures. An application is modeled as a set of tasks, and we consider a fixed-priority preemptive scheduling policy. We target the early design phases, when decisions have a high impact on the subsequent implementation choices. However, due to a lack of information, the early design phases are characterized by uncertainties, e.g., in the worst-case execution times (wcets), or in the functionality requirements. We model uncertainties in the wcets using the “percentile method”. The uncertainties in the functionality requirements are captured using “future scenarios”, which are task sets that model functionality likely to be added in the future. In this context, we derive a mapping of tasks in the application, such that the resulted implementation is both robust and flexible. Robust means that the application has a high chance of being schedulable, considering the wcet uncertainties, whereas a flexible mapping has a high chance to successfully accommodate the future scenarios. We propose a Genetic Algorithm-based approach to solve this optimization problem. Extensive experiments show the importance of taking into account the uncertainties during the early design phases.

This paper presents an approach to the synthesis of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded systems. Our synthesis approach decides the mapping of tasks to processing elements, as well as the voltage and frequency levels for executing each task, such that transient faults are tolerated, the timing constraints of the application are satisfied, and the energy consumed is minimized. Tasks are scheduled using fixed-priority preemptive scheduling, while replication is used for recovery from multiple transient faults. Addressing energy and reliability simultaneously is especially challenging, since lowering the voltage to reduce the energy consumption has been shown to increase the transient fault rate. We presented a Tabu Search-based approach which uses an energy/reliability trade-off model to find reliable and schedulable implementations with limited energy and hardware resources. We evaluated the algorithm proposed using several synthetic and reallife benchmarks.

In this paper, we propose a new system-level design language, called SystemJ. It extends Java with synchronous reactive features present in Esterel and asynchronous constructs suitable for modelling globally asynchronous locally synchronous systems. The strength of SystemJ comes from its ability to offer the data processing and encapsulation elegance of Java, Esterel-like reactivity and synchrony, and the asynchronous de-coupling of CSP all within the Java framework. Using standard Java environments, for specification and modelling, or specialised reactive embedded processors, for high performance implementation, the SystemJ design flow is extremely versatile. With the increasing attention that Java gets in embedded systems, SystemJ comes to address data and control, software and hardware, modelling and implementation in a unified manner

Efficient scheduling mechanisms are essential for implementing real-time operating systems on embedded microprocessors. Reactive processors provide mechanisms and an instruction set architecture more suitable for dealing with external signals than it is the case with traditional interrupts. By extending the reactive framework further we demonstrate simple and efficient hardwareimplemented scheduling of tasks with static priorities. The scheduler support unit is added to the reactive microprocessor core. The real-time scheduler shows substantial improvement of performance over the conventional approach of using prioritized interrupts.

Energy consumption reduction is today an important design issue for all kinds of digital systems. Offering both flexibility and efficient energy management, variable speed processor architectures are prefered for low energy consumption even in hard real-time systems. For this type of systems, the main approach consists in trading speed for lower energy while meeting all deadlines. For tasks with varying execution time, speed scheduling is most efficient if performed at run-time. This paper presents a new ordering technique for such tasks, that reduces the energy consumption resulting from the run-time speed scheduling. Without affecting the real-time behavior, our Uncertainty-Based Scheduling (UBS) is a low complexity but energy-efficient method that can be applied on top of already existent real-time scheduling techniques, such as EDF. These claims are backed up by extensive simulation results accompanied by measurements on a platform based on an Intel 180200 XScale processor.

The work presented in this paper addresses minimization of the energy consumption of a system during system-level design. The paper focuses on scheduling techniques for architectures containing variable supply voltage processors, running dependent tasks. We introduce our new approach for Low-Energy Scheduling (LEneS) and compare it to two other scheduling methods. LEneS is based on a list-scheduling heuristic with dynamic recalculation of priorities, and assumes a given allocation and assignment of tasks to processors. Our approach minimizes the energy by choosing the best combination of supply voltages for each task running on its processor. The set of experiments we present shows that, using the LEneS approach, we can achieve up to 28% energy savings for the tightest deadlines, and up to 77% energy savings when these deadlines are relaxed by 50%.

Article Share on Hard real-time scheduling for low-energy using stochastic data and DVS processors Author: Flavius Gruian Department of Computer Science, Lund University, Box 118, S-221 00 Lund, Sweden Department of Computer Science, Lund University, Box 118, S-221 00 Lund, SwedenView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 46–51https://doi.org/10.1145/383082.383092Online:06 August 2001Publication History 103citation1,122DownloadsMetricsTotal Citations103Total Downloads1,122Last 12 Months23Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access