The spectral correlation density (SCD) function is the time-averaged correlation of two spectral components used for analyzing periodic signals with time-varying spectral content. Although the analysis is extremely powerful, it has not been widely adopted in real-time applications due to its high computational complexity. In this article, we present an efficient FPGA implementation of the FFT accumulation method (FAM) for estimating the SCD function and its alpha profile. The implementation uses a linear systolic array with a bi-directional datapath consisting of DSP-based processing elements (PEs) with a dedicated instruction schedule, achieving a PE utilization of 88.2%. The 128-PE implementation achieves a clock frequency in excess of 530 MHz and consumes 151K LUTs, 151K FFs, 264 BRAMs, 4 URAMs, and 1,054 DSPs, which is less than 36% of the logic fabric on a Zynq UltraScale+ XCZU28DR-2FFVG1517E RFSoC device. It has a modest 12.5W power consumption and an energy efficiency of 4,832 MOPS/W, which is 20.6× better than the published state-of-the-art GPU implementation. In terms of throughput, it achieves 15,340 windows/s (15,340 windows/s × 2,048 samples/window = 31.4 MS/s), which is a 4.65× improvement compared to the above-mentioned GPU implementation and 807× compared to an existing hybrid FPGA-GPU implementation.

Coarse-grained FPGA overlays built around the runtime programmable DSP blocks in modern FPGAs can achieve high throughput and improved scalability compared to traditional overlays built without detailed consideration of FPGA architecture. These overlays can be mapped to using higher level compilers, achieving fast compilation, software-like programmability and run-time management, and high-level design abstraction. OpenCL allows programs running on a host computer to launch accelerator kernels which can be compiled at run-time for a specific architecture, thus enabling portability. However, prohibitive hardware compilation times in traditional design flows mean that the tools cannot effectively use just-in-time (JIT) compilation or runtime performance scaling on FPGAs. We present a methodology for runtime compilation of dataflow graphs expressed as OpenCL kernels onto coarse-grained overlays. The methodology benefits from the high level of abstraction afforded by using the OpenCL programming model, while the mapping to the overlay significantly reduces compilation and load times. Key characteristics of this work include highly performant DSP-optimized functional units that scale to large overlays on modern devices and the ability to perform automatic resource-aware kernel replication up to the size of the overlay. We demonstrate place and route times orders of magnitude better than traditional HLS flows, even when running on an embedded processor in the Xilinx Zynq.

This paper investigates the application of approximate addition in digital image compression. Discrete cosine transform (DCT) is an important operation in digital image compression and we considered utilizing accurate addition and approximate addition separately while calculating the DCT. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders. Accurate and approximate adders were implemented in an ASIC design environment using a 32-28nm CMOS standard cell library and in a FPGA design environment using a Xilinx Artix-7 device. Error analysis has been performed to calculate mean absolute error and root mean square error of approximate adders by considering one million random input vectors. It is observed that approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design metrics compared to the accurate adder. For a FPGA implementation, an optimum approximate adder achieves 8% delay reduction and 19.7% power reduction while consuming 47.6% fewer LUTs and 42.2% fewer flip-flops compared to the accurate FPGA adder. With respect to an ASIC based implementation using standard library cells, an optimum approximate adder achieves 27.1% delay reduction, 46.4% area reduction and 50.3% power reduction compared to a high-speed accurate carry look-ahead adder.

Both computation- and memory-intensiveness of deep learning models have made the deployment of model inference on edge devices with limited resource and energy budget challenging. Non-Volatile Memory (NVM) based in-memory computing has been proposed to reduce data movement as well as energy consumption, which could alleviate the challenge. Racetrack memory is a newly introduced memory technology. It allows high data density fabrication and thus is a good fit for in-memory computing. In order to facilitate the deployment of deep learning models on edge devices, we present an racetrack memory based in-memory integer multiplication, which is one of the core operations in compressed deep learning models. The presented multiplication can be constructed efficiently using racetrack memory technique, and perform the logical operations based on the memory cell with partial reuse of the peripheral circuits. In addition to the multiplication architecture, we also propose and apply a novel write optimization method to the integer multiplication, which transforms the required write operations to shift operations for performance and energy efficiency. The resulting design realizes high area and energy efficiency while maintaining comparable performance with its CMOS counterpart.

Coarse-grained FPGA overlays improve design productivity through software-like programmability and fast compilation. However, the effectiveness of overlays as accelerators is dependent on suitable interface and programming integration into a typically processor-based computing system, an aspect which has often been neglected in evaluations of overlays. We explore the integration of a time-multiplexed FPGA overlay over a server-class PCI Express interface. We show how this integration can be optimised to maximise performance, and evaluate the area overhead. We also propose a user-friendly programming model for such an overlay accelerator system.

This article presents a comprehensive survey of time-multiplexed (TM) FPGA overlays from the research literature. These overlays are categorized based on their implementation into two groups: processor-based overlays, as their implementation follows that of conventional silicon-based microprocessors, and; CGRA-like overlays, with either an array of interconnected processor-based functional units or medium-grained arithmetic functional units. Time-multiplexing the overlay allows it to change its behavior with a cycle-by-cycle execution of the application kernel, thus allowing better sharing of the limited FPGA hardware resource. However, most TM overlays suffer from large resource overheads, due to either the underlying processor-like architecture (for processor-based overlays) or due to the routing array and instruction storage requirements (for CGRA-like overlays). Reducing the area overhead for CGRA-like overlays, specifically that required for the routing network, and better utilizing the hard macros in the target FPGA are active areas of research.

Coarse-grained overlays improve FPGA design productivity by providing fast compilation and software like programmability. Soft processor based overlays with well-defined ISAs are attractive to application developers due to their ease of use. However, these overlays have significant FPGA resource overheads. Time multiplexed (TM) CGRA-like overlays represent an interesting alternative as they are able to change their behavior on a cycle by cycle basis while the compute kernel executes. This reduces the FPGA resource needed, but at the cost of a higher initiation interval (II) and hence reduced throughput. The fully flexible routing network of current CGRA-like overlays results in high FPGA resource usage. However, many application kernels are acyclic and can be implemented using a much simpler linear feed-forward routing network. This paper examines a DSP block based TM overlay with linear interconnect where the overlay architecture takes account of the application kernels' characteristics and the underlying FPGA architecture, so as to minimize the II and the FPGA resource usage. We examine a number of architectural extensions to the DSP block based functional unit to improve the II, throughput and latency. The results show an average 70% reduction in II, with corresponding improvements in throughput and latency.

The distributed minority and majority voting-based redundancy (DMMR) scheme was proposed as an efficient alternative to the conventional N-modular redundancy (NMR) scheme for the design of mission and safety-critical circuits and systems. However, only a basic implementation of the DMMR scheme was considered with no provision for indicating any fault or error in the DMMR system when they might occur. In this context, this paper presents the novel design of a generic system health indicator (SHI) for the DMMR scheme. Compared to the basic DMMR system, the DMMR system with the proposed SHI can provide concurrent information about the state of the system, i.e., whether the system is healthy or not. This helps to improve the observability of the DMMR system which could be useful during the online testing and/or troubleshooting of any faulty zones in the system, pre-emptively or during any scheduled maintenance. Example DMMR systems and their corresponding NMR systems without and with SHI have been implemented using a 32/28nm CMOS process and compared. On average, the DMMR systems with the proposed SHI report 6.5× improvement in a normalized figure of merit compared to the corresponding NMR systems incorporating SHI.

This paper presents a new approximate adder architecture which when implemented on an FPGA consumes fewer logic resources compared to accurate adders of similar size and can achieve higher or comparable operating frequencies. For 32-bit addition, our approximate adder achieves a 25% reduction in the number of LUTs utilized compared to the accurate adder with no compromise on the speed performance. For 64-bit addition, our approximate adder achieves a 24% improvement in the maximum operating frequency, and a 25% reduction in the number of LUTs utilized compared to the accurate adder (post place and route on a Virtex-7 FPGA device). We also make comparisons with the FPGA-based implementations of some well-known gate-level approximate adders, and further provide insights into the error characteristics showing that the proposed approximate adder has a reduced error range.

Asymmetric cryptography algorithms such as RSA are widely used in applications such as blockchain technology and cloud computing to ensure the security and privacy of data. However, the encryption and decryption operations of asymmetric cryptography algorithms involve many computation-intensive multiplications, which require high memory bandwidth and involve large performance and resource overhead. Emerging non-volatile memory technologies such as racetrack memory are regarded to be promising for all levels of memory hierarchy to reduce the area and power overhead due to their high data density and nearly zero leakage. In this paper, we propose an efficient racetrack memory based in-memory design to accelerate the modular multiplication for asymmetric cryptography algorithms. A novel two-stage scalable modular multiplication algorithm is proposed to significantly improve the delay. An efficient architecture is further developed to reduce the number of required adders by half. Experimental results show that our proposed scheme improves the energy efficiency by 45.9%, the area efficiency by 93.6% and achieves 8x of throughput per area compared with the state-of-the-art CMOS-based implementation.

Security is an important concern in cloud computing nowadays. RSA is one of the most popular asymmetric encryption algorithms that are widely used in internet based applications for its public key strategy advantage over symmetric encryption algorithms. However, RSA encryption algorithm is very compute intensive, which would affect the speed and power efficiency of the encountered applications. Racetrack Memory (RM) is a newly introduced promising technology in future storage and memory system, which is perfect to be used in memory intensive scenarios because of its high data density. However, novel designs should be applied to exploit the advantages of RM while avoiding the adverse impact of its sequential access mechanism. In this paper, we present an in-memory Booth multiplier based on racetrack memory to alleviate this problem. As the building block of our multiplier, a racetrack memory based adder is proposed, which saves 56.3% power compared with the state-of-the-art magnetic adder. Integrated with the storage element, our proposed multiplier shows great efficiency in area, power and scalability.

Coarse-grained FPGA overlay architectures paired with general purpose processors offer a number of advantages for general purpose hardware acceleration because of software-like programmability, fast compilation, application portability, and improved design productivity. However, the area overheads of these overlays, and in particular architectures with island-style interconnect, negate many of these advantages, preventing their use in practical FPGA-based systems. Crucially, the interconnect flexibility provided by these overlay architectures is normally over-provisioned for accelerators based on feed-forward pipelined datapaths, which in many cases have the general shape of inverted cones. We propose DeCO, a cone shaped cluster of FUs utilizing a simple linear interconnect between them. This reduces the area overheads for implementing compute kernels extracted from compute-intensive applications represented as directed acyclic dataflow graphs, while still allowing high data throughput. We perform design space exploration by modeling programmability overhead as a function of overlay design parameters, and compare to the programmability overhead of island-style overlays. We observe 87% savings in LUT requirements using the proposed approach compared to DSP block based island-style overlays. Our experimental evaluation shows that the proposed overlay exhibits an achievable frequency of 395 MHz, close to the DSP theoretical limit on the Xilinx Zynq. We also present an automated tool flow that provides a rapid and vendor-independent mapping of the high level compute kernel code to the proposed overlay.

Design productivity and long compilation times are major issues preventing the mainstream adoption of FPGAs in general purpose computing. Several overlay architectures have emerged to tackle these challenges, but at the cost of increased area and performance overheads. This paper examines a coarse grained overlay architecture designed using the flexible DSP48E1 primitive on Xilinx FPGAs. This allows pipelined execution at significantly higher throughput without adding significant area overheads to the PE. We map several benchmarks, using our custom mapping tool, and show that the proposed overlay architecture delivers a throughput of up to 21.6 GOPS and provides an 11 -- 52% improvement in throughput compared to Vivado HLS implementations.

Long term exposure of photovoltaic (PV) systems under relatively harsh and changing environmental conditions can result in fault conditions developing during the operational lifetime. The present solution is for system operators to manually perform condition monitoring of the PV system. However, it is time-consuming, inaccurate and dangerous. Thus, automatic fault detection and diagnosis is a critical task to ensure the reliability and safety in PV systems. The current state-of-the-art techniques either cannot provide enough detailed fault information with high accuracy or have too much complexity. This work presents an automatic fault detection and diagnosis method for string based PV systems. It combines an artificial neural network (ANN) with the conventional analytical method to conduct the fault detection and diagnosis tasks. A two-layered ANN is applied to predict the expected power which is then compared with the measured power from the real PV system. Based on the difference between the ANN estimated power and the measured power, the open circuit voltage and short circuit current of the PV string determined using analytical equations are used to identify any of the six defined fault types. The proposed method has a fast detection, compact structure and good accuracy. Simulation results show the effective fault detection and diagnosis capability of the proposed method.

Cerebellum model articulation controller (CMAC) is an effective localized associative memory that is capable of fast learning and low computational cost. However, it lacks interpretability and has a quantized structure. By incorporating fuzzy logic with CMAC, it gives CMAC interpretable rules and also creates a non-uniform quantized structure. However predefined dimension boundary has to be defined during CMAC creation hence implicitly enforcing a rigid structure. Fuzzy interpolation and extrapolation (FIE) have recently been widely used for sparse rule bases. With the capability of FIE, not only the number of rules used in CMAC can be greatly reduced, it also allows extrapolation with a fuzzy result beyond the rigid CMAC predefined dimension boundary. Encouraging results are discussed in the experimental section.

A switching control strategy is proposed for single inductor current-fed push-pull converter with a secondary side active voltage doubler rectifier or a voltage rectifier used in photovoltaic (PV) grid interfacing. The proposed switching control strategy helps to turn-on and turn-off the primary side power switches with zero-voltage and zero-current switching. The operation of the push-pull converter is analyzed for two modes of operation. The feasibility of the proposed switching control strategy is validated using simulation and experimental results.

DSP blocks in modern FPGAs can be used for a wide range of arithmetic functions, offering increased performance while saving logic resources for other uses. They have evolved to better support a plethora of signal processing tasks, meaning that in other application domains they may be underutilised. The DSP48E1 primitives in new Xilinx devices support dynamic programmability that can help extend their usefulness; the specific function of a DSP block can be modified on a cycle-by-cycle basis. However, the standard synthesis flow does not leverage this flexibility in the vast majority of cases. The lean DSP Extension Architecture (iDEA) presented in this article builds around the dynamic programmability of a single DSP48E1 primitive, with minimal additional logic to create a general-purpose processor supporting a full instruction-set architecture. The result is a very compact, fast processor that can execute a full gamut of general machine instructions. We show a number of simple applications compiled using an MIPS compiler and translated to the iDEA instruction set, comparing with a Xilinx MicroBlaze to show estimated performance figures. Being based on the DSP48E1, this processor can be deployed across next-generation Xilinx Artix-7, Kintex-7, Virtex-7, and Zynq families.

Reconfigurable architectures have found use in a wide range of application domains, but mostly as static accelerators for computationally intensive functions. Commodity computing adoption has not taken off due primarily to design complexity challenges. Yet reconfigurable architectures offer significant advantages in terms of sharing hardware between distinct isolated tasks, under tight time constraints. Trends towards amalgamation of computing resources in the automotive and aviation domains have so far been limited to non-critical systems, because processor approaches suffer from a lack of predictability and isolation. Hybrid reconfigurable platforms may provide a promising solution to this, by allowing physically isolated access to hardware resources, and support for computationally demanding applications, but with improved programmability and management. We propose virtualized execution and management of software and hardware tasks using a microkernel-based hypervisor running on a commercial hybrid computing platform (the Xilinx Zynq). We demonstrate a framework based on the CODEZERO hypervisor, which has been modified to leverage the capabilities of the FPGA fabric. It supports discrete hardware accelerators, dynamically reconfigurable regions, and regions of virtual fabric, allowing for application isolation and simpler use of hardware resources. A case study demonstrating multiple independent (and isolated) software and hardware tasks is presented.

Maximum power point tracking (MPPT) is considered as an important strategy to increase the power output from photovoltaic (PV) systems. The presence of multiple maximum power points (MPPs) under partially shaded conditions (PSC) means that traditional MPPT algorithms, such as perturb and observe (P&O) and incremental conductance (IncCond), are unable to effectively track the global MPP. Other existing MPPT methods are either too complex or need additional equipment. In this paper, we propose a simple and efficient hybrid MPPT algorithm for PV systems working under PSC. It combines the advantages of P&O (or IncCond) and artificial neural network (ANN)-based MPPT methods, and features a relatively lower cost, fast response, and simple structure. In this hybrid MPPT, the ANN is used to initially categorize the power based on the irradiance pattern. Based on the classified category, an initial reference duty ratio is determined. Subsequently, a conventional MPPT algorithm (such as P&O or IncCond) is used to search near the global MPP. Finally, the system is able to accurately determine the global MPP which consequently increases the power output from the PV array. The effectiveness of the proposed hybrid MPPT, under various shading patterns, is verified using both simulations and an experimental setup.

A high-frequency-link micro-inverter is proposed for integrating a single photovoltaic panel to a local load or utility grid. The number of power switches is minimized in addition to reduced magnetic components in order to design a low cost, light weight, compact and efficient inverter. A front-end current-fed isolated boost converter is used to integrate the photovoltaic panel to the rest of micro-inverter that consists of a half-wave cycloconverter and half-bridge inverter. The two basic building modules are interconnected via a high voltage DC-link capacitor. A series resonant tank is used to implement soft-switching in the half-bridge inverter and in the half-wave cycloconverter at the grid side. A highly optimized switching scheme is proposed to have soft-switching in all possible power conversion stages. The proposed micro-inverter is simulated using the MATLAB/Simulink Simpower block-set and with PSIM in order to verify the feasibility of the proposed converter and the effectiveness of the proposed switching control scheme.

BACKGROUND: The rapid growth of short read datasets poses a new challenge to the short read mapping problem in terms of sensitivity and execution speed. Existing methods often use a restrictive error model for computing the alignments to improve speed, whereas more flexible error models are generally too slow for large-scale applications. A number of short read mapping software tools have been proposed. However, designs based on hardware are relatively rare. Field programmable gate arrays (FPGAs) have been successfully used in a number of specific application areas, such as the DSP and communications domains due to their outstanding parallel data processing capabilities, making them a competitive platform to solve problems that are "inherently parallel". RESULTS: We present a hybrid system for short read mapping utilizing both FPGA-based hardware and CPU-based software. The computation intensive alignment and the seed generation operations are mapped onto an FPGA. We present a computationally efficient, parallel block-wise alignment structure (Align Core) to approximate the conventional dynamic programming algorithm. The performance is compared to the multi-threaded CPU-based GASSST and BWA software implementations. For single-end alignment, our hybrid system achieves faster processing speed than GASSST (with a similar sensitivity) and BWA (with a higher sensitivity); for pair-end alignment, our design achieves a slightly worse sensitivity than that of BWA but has a higher processing speed. CONCLUSIONS: This paper shows that our hybrid system can effectively accelerate the mapping of short reads to a reference genome based on the seed-and-extend approach. The performance comparison to the GASSST and BWA software implementations under different conditions shows that our hybrid design achieves a high degree of sensitivity and requires less overall execution time with only modest FPGA resource utilization. Our hybrid system design also shows that the performance bottleneck for the short read mapping problem can be changed from the alignment stage to the seed generation stage, which provides an additional requirement for the future development of short read aligners.

BLAST is one of the most popular sequence analysis tools used by molecular biologists. It is designed to efficiently find similar regions between two sequences that have biological significance. However, because the size of genomic databases is growing rapidly, the computation time of BLAST, when performing a complete genomic database search, is continuously increasing. Thus, there is a clear need to accelerate this process. In this paper, we present a new approach for genomic sequence database scanning utilizing reconfigurable field programmable gate array (FPGA)-based hardware. In order to derive an efficient structure for BLASTN, we propose a reconfigurable architecture to accelerate the computation of the word-matching stage. The experimental results show that the FPGA implementation achieves a speedup around one order of magnitude compared to the NCBI BLASTN software running on a general purpose computer.

As Field Programmable Gate Arrays (FPGAs) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for FPGA adoption, so FPGA vendors tailored their architectures to such applications. The resulting embedded digital signal processing (DSP) blocks have now advanced to the point of supporting a wide range of operations. In this paper, we explore how these DSP blocks can be applied to general computation. We show that the DSP48E1 blocks in Xilinx Virtex-6 devices support a wide range of standard processor instructions which can be designed into the core of a basic processor with minimal additional logic usage.

The explosive growth of short read datasets produced by high throughput DNA sequencing technologies poses a challenge to the mapping of short reads to a reference genome in terms of sensitivity and execution speed. Existing methods often use a restrictive error model for computing the alignments to improve speed, whereas more flexible error models are generally too slow for large-scale applications. Although a number of short read mapping software tools have been proposed, designs based on hardware are relatively rare. In this paper, we present a hybrid system for short read mapping utilizing both software and field programmable gate array (FPGA)-based hardware. The compute intensive semi-global alignment operation is accelerated on the FPGA. The proposed FPGA aligner is implemented with a parallel block structure to gain computational efficiency. We also propose a block-wise alignment algorithm to approximate the score of the conventional dynamic programming algorithm. Our performance comparison shows that the FPGA achieves an average speedup of 38 for the alignment operation on a Xilinx Virtex5 FPGA compared to the GASSST software implementation. For the overall execution time, our hybrid system achieves an average speedup of 2.4 compared to GASSST at comparable sensitivity and an average speedup of 1.8 compared to the popular BWA software at a significantly better sensitivity.

The rapid growth of short read datasets poses a new challenge to the mapping of short reads to a reference genome in terms of sensitivity and execution speed. In this work, we present a parallel architecture for short read mapping utilizing field programmable gate array (FPGA)-based hardware. The computation intensive semi-global alignment and the hash table lookup operations are mapped onto an FPGA. The proposed Align Core is implemented with a parallel block structure to gain computational efficiency. We present a new parallel block-wise alignment structure to approximate the conventional dynamic programming algorithm. The performance of our FPGA aligner is compared to the GASSST and BWA software implementations. In terms of the overall execution time, our FPGA aligner achieves a speedup between 3.4 to 6.7 compared to GASSST with a comparable sensitivity and a speedup between 2.5 to 5.2 compared to BWA at a higher sensitivity.

This paper presents a very lean DSP Extension Architecture (iDEA) soft processor for Field Programmable Gate Arrays (FPGAs). iDEA has been built to be as lightweight as possible, utilising the run-time flexibility of the DSP48E1 primitive in Xilinx FPGAs to serve as many processor functions as possible. We show how the primitive's flexibility can be leveraged within a general-purpose processor, what additional circuitry is needed, and present a full instruction-set architecture. The result is a very compact processor that can run at high speed, while executing a full gamut of general machine instructions. We provide results for a number of simple applications, and show how the processor's resource requirements and frequency compare to a Xilinx MicroBlaze soft core. Based on the DSP48E1, this processor can be deployed across next-generation Xilinx Artix-7, Kintex-7, and Virtex-7 families.

In order to increase the efficiency of the Photovoltaic (PV) system, the PV system should be operated at the Maximum Power Point (MPP). The MPP Tracking (MPPT) is an essential part in achieving this improvement. Some of the existing techniques such as Perturb-and-Observe (P&O) and Incremental Conductance (INC) are relatively simpler to implement, but under rapidly changing irradiance and temperature conditions, they fail to track the MPP. Although methods such as Multilayer Perceptron (MLP) and Fuzzy Logic (FL) are efficient in tracking the MPP, their implementation increases the system complexity. In this paper, we propose a novel artificial intelligence based controller for MPPT, which can efficiently track the MPP, while keeping the computational complexity within the limits. Our technique uses Functional Link Artificial Neural Network (FLANN) to predict the PV output voltage at the MPP. Since there is no hidden layer, FLANN is computationally inexpensive. Simulation results verify that the proposed FLANN controller is computationally less intensive and exhibits higher efficiency under rapidly changing weather conditions.

This paper presents a Chebyshev Functional Link Neural Network (CFLNN) based model for photovoltaic modules. There are two basic approaches to build a model - use an analytical modeling technique or use an Artificial Neural Network (ANN) based method. However, both the analytical modeling technique and the traditional Multilayer Perceptron (MLP) model have some disadvantages. For example, in the analytical model, the influence of irradiance and temperature on some parameters of the photovoltaic module, such as the parallel and series resistance and other uncertainty factors, are not taken into consideration. In the case of the multilayer neural network model, there is a large computational complexity in training the network and in its implementation. In order to overcome these advantages, we propose a CFLNN based model for solar modules. The proposed model not only reduces the complexity of the network due to the absence of hidden layers in the network configuration, but also shows better accuracy over the analytical modeling method. In the experimental section, the operating current predicted by CFLNN is compared with the outputs from other two modeling methods - MLP and the two-diode model. Finally, verification is performed using experimental datasets. The results show that the CFLNN modeling method provides better prediction of the output current compared to the analytical model and has a reduced computational complexity than the traditional MLP model.

MOTIVATION: New high-throughput sequencing technologies have promoted the production of short reads with dramatically low unit cost. The explosive growth of short read datasets poses a challenge to the mapping of short reads to reference genomes, such as the human genome, in terms of alignment quality and execution speed. RESULTS: We present CUSHAW, a parallelized short read aligner based on the compute unified device architecture (CUDA) parallel programming model. We exploit CUDA-compatible graphics hardware as accelerators to achieve fast speed. Our algorithm uses a quality-aware bounded search approach based on the Burrows-Wheeler transform (BWT) and the Ferragina-Manzini index to reduce the search space and achieve high alignment quality. Performance evaluation, using simulated as well as real short read datasets, reveals that our algorithm running on one or two graphics processing units achieves significant speedups in terms of execution time, while yielding comparable or even better alignment quality for paired-end alignments compared with three popular BWT-based aligners: Bowtie, BWA and SOAP2. CUSHAW also delivers competitive performance in terms of single-nucleotide polymorphism calling for an Escherichia coli test dataset. AVAILABILITY: http://cushaw.sourceforge.net

Thermal aware scheduling (TAS) is an important system level optimization for many-core systems. A fast event driven thermal estimation method, which includes both the dynamic and leakage power models, for monitoring temperature and guiding dynamic TAS (DTAS) is proposed in this paper. The fast event driven thermal estimation is based upon a thermal map, with occasional thermal sensor-based calibration, which is updated only when a high level event occurs. To minimize the overhead, while maintaining the estimation accuracy, prebuilt look-up-tables and predefined leakage calibration parameters are used to speed up the thermal solution. Experimental results show our method is accurate, producing thermal estimations of similar quality to an existing open-source thermal simulator, while having a considerably reduced computational complexity. Based on this predictive approach, we take full advantage of a projected future thermal map to develop several heuristic policies for DTAS. We show that our proposed predictive policies are significantly better, in terms of minimizing average/peak temperature, reducing the dynamic thermal management overhead and improving other real-time features, than existing DTAS schedulers, making them highly suitable for heuristically guiding thermal aware task allocation and scheduling.

External quantum efficiency (EQE) of a solar cell is an important parameter as it determines the design efficiency and overall conversion efficiency. The EQE of solar cells for space applications is adversely affected due to bombardment of charged particles in space. Numerical model based softwares, e.g., PC1D, can be used to estimate the EQE under such situation. By varying the cell parameters to fit the measured EQE one can obtain degradation performance of space solar cells. However, due to complex phenomena and interactions occurring between the junctions of the solar cells and the nonlinear influence of charged particles, the accuracy of these models may be limited. In this paper we propose an artificial neural network (ANN)-based model to estimate the EQE performance of triple junction InGaP/GaAs/Ge solar cells under the influence of wide range of charged particles. With extensive simulation results we have shown that the ANN-based models provide better estimate of the EQE in terms of mean square error and correlation coefficient than the results reported by Sato et al.

UNLABELLED: CompleteMOTIFs (cMOTIFs) is an integrated web tool developed to facilitate systematic discovery of overrepresented transcription factor binding motifs from high-throughput chromatin immunoprecipitation experiments. Comprehensive annotations and Boolean logic operations on multiple peak locations enable users to focus on genomic regions of interest for de novo motif discovery using tools such as MEME, Weeder and ChIPMunk. The pipeline incorporates a scanning tool for known motifs from TRANSFAC and JASPAR databases, and performs an enrichment test using local or precalculated background models that significantly improve the motif scanning result. Furthermore, using the cMOTIFs pipeline, we demonstrated that multiple transcription factors could cooperatively bind to the upstream of important stem cell differentiation regulators. AVAILABILITY: http://cmotifs.tchlab.org.

BACKGROUND: Next-generation sequencing technologies have led to the high-throughput production of sequence data (reads) at low cost. However, these reads are significantly shorter and more error-prone than conventional Sanger shotgun reads. This poses a challenge for the de novo assembly in terms of assembly quality and scalability for large-scale short read datasets. RESULTS: We present DecGPU, the first parallel and distributed error correction algorithm for high-throughput short reads (HTSRs) using a hybrid combination of CUDA and MPI parallel programming models. DecGPU provides CPU-based and GPU-based versions, where the CPU-based version employs coarse-grained and fine-grained parallelism using the MPI and OpenMP parallel programming models, and the GPU-based version takes advantage of the CUDA and MPI parallel programming models and employs a hybrid CPU+GPU computing model to maximize the performance by overlapping the CPU and GPU computation. The distributed feature of our algorithm makes it feasible and flexible for the error correction of large-scale HTSR datasets. Using simulated and real datasets, our algorithm demonstrates superior performance, in terms of error correction quality and execution speed, to the existing error correction algorithms. Furthermore, when combined with Velvet and ABySS, the resulting DecGPU-Velvet and DecGPU-ABySS assemblers demonstrate the potential of our algorithm to improve de novo assembly quality for de-Bruijn-graph-based assemblers. CONCLUSIONS: DecGPU is publicly available open-source software, written in CUDA C++ and MPI. The experimental results suggest that DecGPU is an effective and feasible error correction algorithm to tackle the flood of short reads produced by next-generation sequencing technologies.

BACKGROUND: Next-generation sequencing technologies have given rise to the explosive increase in DNA sequencing throughput, and have promoted the recent development of de novo short read assemblers. However, existing assemblers require high execution times and a large amount of compute resources to assemble large genomes from quantities of short reads. RESULTS: We present PASHA, a parallelized short read assembler using de Bruijn graphs, which takes advantage of hybrid computing architectures consisting of both shared-memory multi-core CPUs and distributed-memory compute clusters to gain efficiency and scalability. Evaluation using three small-scale real paired-end datasets shows that PASHA is able to produce more contiguous high-quality assemblies in shorter time compared to three leading assemblers: Velvet, ABySS and SOAPdenovo. PASHA's scalability for large genome datasets is demonstrated with human genome assembly. Compared to ABySS, PASHA achieves competitive assembly quality with faster execution speed on the same compute resources, yielding an NG50 contig size of 503 with the longest correct contig size of 18,252, and an NG50 scaffold size of 2,294. Moreover, the human assembly is completed in about 21 hours with only modest compute resources. CONCLUSIONS: Developing parallel assemblers for large genomes has been garnering significant research efforts due to the explosive size growth of high-throughput short read datasets. By employing hybrid parallelism consisting of multi-threading on multi-core CPUs and message passing on compute clusters, PASHA is able to assemble the human genome with high quality and in reasonable time using modest compute resources.

Thermal aware scheduling (TAS) is an important system level optimization for CMP and MPSoC. An event driven thermal estimation method which can assist dynamic TAS is proposed in this paper. The event driven thermal estimation is based upon a thermal map which is updated only when a high level event occurs. To minimize the overhead, while maintaining the estimation accuracy, the prebuilt look-up-tables and the superposition principle are used to speed up the solution of the thermal RC network. Experimental results show our method is accurate, producing thermal estimations of similar quality to existing thermal simulators, while having a considerably reduced computational complexity. Our event driven thermal estimation technique is significantly better, in terms of accuracy, than existing TAS schedulers, making it highly suitable for integration into the OS kernel.

Reconfigurable computing is an exciting new area of research. It opens up a number of new computing paradigms with the potential to significantly change the embedded computing landscape. Unfortunately, as with any new concept, there is much to be done before it can be brought into the mainstream. Reconfigurable computing needs to be made more usable by the general computing community by making the application mapping process more user transparent. We need to be able to efficiently exploit the parallelism and high communications bandwidth available in reconfigurable computing systems, such as provided by FPGA devices. In this paper we propose a framework to map C-based applications to an FPGA based system. The framework relies on dependency based analysis information obtained from a high level Intermediate Representation (IR) of the C-Application. The dependencies have a major impact on the instruction flow and the parallelism of the algorithms when implemented on FPGA based high performance computing platforms. We demonstrate the importance of these dependencies in algorithms by examining a compute intensive bio-informatics application. Targeting on a Xilinx Virtex 5 XC5VFX70T FPGA, our place and route results achieved 92% of the clock frequency achieved by using a manual design of the same application. The contribution in this paper is to provide a semi-automated approach to generate hardware for FPGA based systems through a high level data dependency graphical IR.

MOTIVATION: Multiple sequence alignment is of central importance to bioinformatics and computational biology. Although a large number of algorithms for computing a multiple sequence alignment have been designed, the efficient computation of highly accurate multiple alignments is still a challenge. RESULTS: We present MSAProbs, a new and practical multiple alignment algorithm for protein sequences. The design of MSAProbs is based on a combination of pair hidden Markov models and partition functions to calculate posterior probabilities. Furthermore, two critical bioinformatics techniques, namely weighted probabilistic consistency transformation and weighted profile-profile alignment, are incorporated to improve alignment accuracy. Assessed using the popular benchmarks: BAliBASE, PREFAB, SABmark and OXBENCH, MSAProbs achieves statistically significant accuracy improvements over the existing top performing aligners, including ClustalW, MAFFT, MUSCLE, ProbCons and Probalign. Furthermore, MSAProbs is optimized for multi-core CPUs by employing a multi-threaded design, leading to a competitive execution time compared to other aligners. AVAILABILITY: The source code of MSAProbs, written in C++, is freely and publicly available from http://msaprobs.sourceforge.net.

The importance of cognitive skills in human learning and reasoning has become well established in recent years. This motivates the search for a knowledge representation that supports the development of a computational algorithm that performs, as well as instructs such cognitive skills. Cognitive skills can be broadly divided into two types: specific and generic cognitive skills. Intelligent tutoring systems (ITSs) that develop generic cognitive skills are essential for developing classification, generalization, and comparison processes. However, these current systems are inherently open loop and do not utilize feedback, based on the student's competence level, to adapt the learning process. This is a major drawback when attempting to provide a dynamic learner-focused approach for effective instruction. In this paper, we present EpiList II, an ITS that closes the loop and is hence able to monitor and dynamically assess the student's cognitive-skill competence. The results show a significant improvement in positive- and negative-reasoning skills, with 51% of students (up from an average of 8% of students when using an open-loop ITS) acquiring/developing these skills.

Progressive alignment is a widely used approach for computing multiple sequence alignments (MSAs). However, aligning several hundred or thousand sequences with popular progressive alignment tools such as ClustalW requires hours or even days on state-of-the-art workstations. This paper presents MSA-CUDA, a parallel MSA program, which parallelizes all three stages of the ClustalW processing pipeline using CUDA and achieves significant speedups compared to the sequential ClustalW for a variety of large protein sequence datasets. Our tests on a GeForce GTX 280 GPU demonstrate average speedups of 36.91 (for long protein sequences), 18.74 (for average-length protein sequences), and 11.27 (for short protein sequences) compared to the sequential ClustalW running on a Pentium 4 3.0 GHz processor. Our MSA-CUDA outperforms ClustalW-MPI running on 32 cores of a high performance workstation cluster.

Thermal aware scheduling (TAS) is an important system level solution for dealing with the thermal issues on CMP. We propose a TAS algorithm based on look up tables to allow the rapid calculation of the post-thermal map from the current thermal profile. We propose two different metrics for determining where to place the task: one based on the maximum core temperature in the post-thermal map; and another based on the sum of the product of the post-thermal map temperature and the remaining task runtime for each core. Experimental results show that our algorithms are better, particularly for high power applications, at minimizing the peak/average temperature, and are able to achieve an average rejection ratio of about 30% to 50% of that chieved by existing algorithms from the literature.

Computing large multiple protein sequence alignments using progressive alignment tools such as ClustalW requires several hours on state-of-the-art workstations. ClustalW uses a three-stage processing pipeline: (i) pairwise distance computation; (ii) phylogenetic tree reconstruction; and (iii) progressive multiple alignment computation. Previous work on accelerating ClustalW was mainly focused on parallelizing the first stage and achieved good speedups for a few hundred input sequences. However, if the input size grows to several thousand sequences, the second stage can dominate the overall runtime. In this paper, we present a new approach to accelerating this second stage using graphics processing units (GPUs). In order to derive an efficient mapping onto the GPU architecture, we present a parallelization of the neighbor-joining tree reconstruction algorithm using CUDA. Our experimental results show speedups of over 26times for large datasets compared to the sequential implementation.

Molecular biologists use hidden Markov models (HMMs) as a popular tool to statistically describe biological sequence families. This statistical description can then be used for sensitive and selective database scanning, e.g., new protein sequences are compared with a set of HMMs to detect functional similarities. Efficient dynamic-programming algorithms exist for solving this problem; however, current solutions still require significant scan times. These scan time requirements are likely to become even more severe due to the rapid growth in the size of these databases. This paper shows how reconfigurable architectures can be used to derive an efficient fine-grained parallelization of the dynamic programming calculation. We describe how this technique leads to significant runtime savings for HMM database scanning on a standard off-the-shelf field-programmable gate array (FPGA).

This paper investigates the design of very low complexity multiplierless linear phase FIR filters for use in the channelizer of multi-standard software defined radios. A technique for reducing the hardware complexity of linear phase FIR digital filters which minimizes the adder depth and the number of adders in the multiplier block is introduced and is used to implement a multistage, multi-standard decimating filter. The design reuses components for different communications standards and is thus ideal for use in systems which support dynamic reconfiguration.

A novel fuzzy-neural network, the type-2 GA- TSKfnn (T2GA-TSKfnn), combining a type-2 fuzzy logic system (FLS) and a genetic algorithm (GA) based Takagi-Sugeno- Kang fuzzy neural network (GA-TSKfnn), is presented. The rational for this combination is that type-2 fuzzy sets are better able to deal with rule uncertainties, while the optimal GA-based tuning of the T2GA-TSKfnn parameters achieves better classification results. However, a general T2GA-TSKfnn is computationally very intensive due to the complexity of the type-2 to type-1 reduction. Therefore, we adopt an interval T2GA-TSKfnn implementation to simplify the computational process. Simulation results are provided to compare the T2GA-TSKfnn against other fuzzy neural networks. These results show that the proposed system is able to achieve a higher classification rate when compared against a number of other traditional neuro-fuzzy classifiers.

This paper proposes a fast algorithm to enumerate all convex subgraphs that satisfy the I/O constraints from the dataflow graph (DFG) of a basic block. The algorithm can be tuned to determine all subgraphs or only those connected subgraphs. This allows a choice between better instruction-set extension (ISE) and faster design space exploration. The algorithm uses a grading method to identify the next node for inclusion into a subgraph. If the selected node is included, other related nodes are included as well, thus ensuring that the resultant subgraph is always convex and at the same time, reducing the problem size by a block of nodes. If the selected node is not included, the DFG will be split into smaller DFGs, thus reducing also the problem size. With this as base, the algorithm employs a simple but efficient method to prune the invalid subgraphs that violate the I/O constraints. Results show that for relatively small DFGs with small exploration space, the new algorithm has similar runtimes to that of existing algorithms. However, for larger DFGs with much larger exploration space and with multiple input and output constraints, the runtime improvement can be orders of magnitude better than that of existing algorithms. The new algorithm can be used to quickly identify custom instructions for ISE of embedded processors

A novel fuzzy neural network architecture, the approximate analogical reasoning based fuzzy CMAC (FCMAC-AARS), is proposed. AARS is incorporated into the fuzzy CMAC structure as it is conceptually clearer and more computationally efficient than the CRI and TVR fuzzy inference schemes. A prediction and trading framework has been proposed which exploits the price percentage oscillator (PPO) for input preprocessing and trading decision making. Numerical experiments conducted on real-life stock data confirm the validity of the design and the performance of the FCMAC-AARS system.

Bank failure prediction is important to bank regulators, including central banks and financial ministries. Off-site surveillance systems or early warning models use financial statements or other rating systems to assess the financial status of the banks. Statistical based bank failure prediction models assume a normal probability distribution and equal dispersion on the data that is often violated. Neural network (NN) based models do not make these assumptions about the data. NNs give better prediction results, however, they lack explanatory capabilities. Fuzzy-neural networks (FNN), allow explanatory capabilities and give better performance. In this paper, several bank failure prediction models using the pseudo outer product-based FNN with a compositional rule of inference and singleton fuzzifier (POPFNN-CRI(S)) are proposed. The system uses financial covariates derived from publicly available financial statements to predict failing banks. The performances of the models are assessed through the classification of 3636 US banks for one-year and two-year periods. As it is not possible to obtain all financial statements, we also propose a model to aid in the reconstruction of missing financial data using POPFNN-CRI(S). To complete the study, the effect that missing data has on the outcome of bank failure prediction is examined.

This paper explores the use of pre-routed cores as execution objects in an object-oriented programming model and execution environment for dynamic computing on FPGA. In order to maintain FPGA computing performance it is crucial to thoroughly analyze the issues at the lowest level of device detail in order to ensure that computing circuit encapsulation is as efficient as possible. The first methodology that allows a core to scale its interface bandwidth to the maximum available in a routing channel was presented. Cores can be constructed independently from the rest of the system using a framework that is independent of the method used to place and route primitive components within the core. The authors used an architecture model and CAD tools that mirror those used in industry. Abutting cores are instantly connected by co-location of interface wires. Eliminating run-time routing drastically reduces the time taken to construct a system using a set of cores. It was illustrated how, although pre-routing has an adverse impact on core performance by up to 14%, it can improve functional density by up to six times for rapid reconfiguration

Recent advancements in mixed hardware-software modeling platforms have simplified the process of concurrently modeling complex algorithms in hardware while considering the software generation in an integrated environment. To efficiently facilitate design space exploration for RISC extensible processors, it is imperative to use a tightly coupled hardware-software co-design and modeling effort that also maintains the flexibility for exploring other types of microarchitectures. We have introduced a simulation framework using a software-oriented design methodology that can be adopted to model the software and hardware components in a reconfigurable co-processor. Experiments on some commonly used DSP and image processing tasks show that hardware-software trade-offs in the various models can be efficiently analyzed during the initial design phase.

We propose an algorithm for reducing the hardware complexity of linear phase FIR digital filters without resorting to an increase in the number of adder steps in the multiplier block adders. We aggressively reduce both the coefficient wordlength and the number of non-zero bits in the filter coefficients so that the adder step can be minimized. The hardware implementation of the coefficients is such that the number of full adders is proportional to the product of the input signal wordlength and the number of adders. That is, in general, the number of full adders is independent of the coefficient wordlength and the number of shifts between nonzero bits in the coefficient. Results show that the proposed technique achieves a 67% and 71% reduction in the number of multiplier block adders and the number of multiplier block full adders respectively. Our technique has been successfully applied to filters with up to 500 taps.

Protein sequences with unknown functionality are often compared to a set of known sequences to detect functional similarities. Efficient dynamic-programming algorithms exist for solving this problem, however current solutions still require significant scan times. These scan time requirements are likely to become even more severe due to exponential database growth. In this paper we present a new approach to bio-sequence database scanning using re-configurable FPGA-based hardware platforms to gain high performance at low cost. Efficient mappings of the Smith-Waterman algorithm using fine-grained parallel processing elements (PEs) that are tailored towards the parameters of a query have been designed. We use customization opportunities available at run-time to dynamically hyper customize the systolic array to make better use of available resource. Our FPGA implementation achieves a speedup of approximately 170 for linear gap penalties and 125 for affine gap penalties as compared to a standard desktop computing platform. We show how hyper-customization at run-time can be used to further improve the performance.

Summary: Aligning hundreds of sequences using progressive alignment tools such as ClustalW requires several hours on state-of-the-art workstations. We present a new approach to compute multiple sequence alignments in far shorter time using reconfigurable hardware. This results in an implementation of ClustalW with significant runtime savings on a standard off-the-shelf FPGA. Availability: An online server for ClustalW running on a Pentium IV 3 GHz with a Xilinx XC2V6000 FPGA PCI-board is available at http://beta.projectproteus.org. The PE hardware design in Verilog HDL is available on request from the first author. Contact: [email protected]