Gallium Nitride (GaN) platforms are reshaping the efficiency, frequency, and form factor of power electronics integrated circuits. However, the absence of p-channel transistors of GaN technologies makes traditional electrostatic discharge (ESD) protection for integrated circuits (ICs) ineffective. This letter proposes a protection network for input/output pins that leverages the unique conduction properties of enhancement-mode GaN transistors in the third quadrant of their current-voltage (I-V) plane. Experimental measurements confirm the viability of the proposed solution as a library element of the process design kit.

This paper presents the design and experimental measurement of a fully integrated gate driver fabricated together with a 200-V GaN power switch in a GaN-on-SOI technology. The driver exploits 20-V low-voltage enhancement-mode HEMTs (E-HEMTs), Metal-Insulator-Metal (MIM) bootstrap capacitors and two-dimensional electron gas (2DEG) resistors. To overcome the inherent lack of p-channel devices in the GaN technology, the design employs the bootstrapping approach which allows for full turn-on of the 200-V power GaN switch while minimizing static power consumption. Furthermore, the relatively high breakdown voltage (20 V) of the low-power E-HEMTs allows them to withstand the high voltages generated during bootstrapping. Static power consumption is further reduced by minimizing the number of ratioed logic inverters and implementing an anti-cross-conduction network to eliminate cross-conduction switching losses. The design also leverages the third quadrant of the HEMTs’$I_{\mathrm{DS}}-V_{\mathrm{DS}}$characteristic to emulate the diode behavior, potentially reducing external component requirements. Measured performance reveals an average gate driver current consumption ranging from$370 \mu \mathrm{~A}$at -40°C to$150 \mu \mathrm{~A}$at 150°C. Additionally, the rise and fall times when driving the power switch with 365-m$\Omega$on-resistance are respectively 6.5 ns and 3.5 ns at room temperature.

Modern high-performance electronics is pushing Si technology to its limits. Gallium Nitride (GaN) emerges as a promising alternative due to its superior properties in high-frequency and high-power applications. To fully utilize the fast-switching ability of the GaN technology, monolithic integration is a key. A monolithically integrated GaN power IC (Integrated Circuit) reduces the inductive parasitic enabling a fast efficient switching operation. However, GaN basic building blocks, particularly operational amplifiers (Op-Amps), face severe challenges due to the limitations of the GaN technology. This paper presents the first three-stage Op-Amp for high-performance feedback circuits realized in the IMEC’s 200-V GaN-IC technology on a GaN-on-SOI (Silicon on Insulator) substrate. The design utilizes a cascade of three differential stages resistively loaded to achieve a nearly 60-dB DC gain and 25-MHz gain-bandwidth and implements a novel dual single-Miller frequency compensation technique to provide closed-loop stability. The Op-Amp offers a Slew Rate exceeding 70 V/μs with 1% settling time of about 120 ns at room temperature. The correct circuit functionality from −40 °C to 150 °C was demonstrated through simulations and experimental test.

This paper presents a 0.4-V bulk-driven two-stage operational transconductance amplifier (OTA) achieving an exceptionally high voltage gain exceeding 120 dB without requiring additional bias voltages. This is accomplished using a self-cascode composite transistor configuration. Common-mode and power-supply rejection ratios ( CMRR and PSRR, respectively) exceeding 90 dB are achieved through input stage optimization. An intrinsic current-buffer Miller compensation technique is also employed to enhance frequency performance. Compared to state-of-the-art designs, the proposed OTA exhibits superior performance in terms of gain-bandwidth trade-off, settling time, PSRR, and robustness against variations. This is demonstrated through extensive measurements across corner wafers and temperature within the range of -20∘C to 100∘C (unavailable in prior art).

A nanopower, buffered CMOS voltage reference designed to operate across the entire industrial temperature range (from$- 40~^{\circ }$C to$125~^{\circ }$C) and with an input voltage range from 1.2 to 5 V (automotive applications) is presented. The solution provides 390 mV at$20~^{\circ }$C and is implemented in a standard BCD technology featuring 160-nm CMOS devices. It is characterized by an average temperature coefficient of 200 ppm/°C, a line sensitivity (LS) of 0.138%/V, and a power supply rejection of −83 dB at 100 Hz. In addition, the circuit occupies a die area of 0.146 mm2 (with the reference circuit alone covering 0.043 mm2) and maintains a highly stable current consumption of around 45 nA across various process and input voltage conditions (25 nA for the reference circuit alone) while providing a maximum output current of$630~\mu $A with a load regulation of 0.016 mV/$\mu $A.

This study presents a low-voltage bulk-driven CMOS operational transconductance amplifier (OTA) operating in the subthreshold region designed to drive loads up to 10 nF, which is the largest value for this class of amplifiers. To meet this goal, the solution exploits the body terminal of various active devices leveraging local positive feedback to enhance the input transconductance gain and implementing dynamic threshold voltage control in the output transistors. This, along with a Slew Rate Enhancer section, significantly improves the OTA current driving capability. Experimental measurements conducted on a prototype, implemented in a 60-nm technology and supplied from 0.35 V, confirm the expected performance demonstrating a SR of 1.1 V/ms for a 10-nF load with a limited quiescent current consumption of 1.4$\mu$A.

This paper presents for the first time a fully integrated galvanic isolation interface in a GaN technology. It is based on planar micro-antennas and chip-to-chip communication with an on-off keying-modulated RF carrier. This approach can achieve high isolation rating and high common-mode transient immunity by properly setting the distance between chips. The interface provides the isolation channel for a main driver/power switch and the one for the control feedback of the dc-dc converter providing the isolated power supply. Driver and power control channels adopt an RF carrier of 2 GHz and 1.2 GHz, which are modulated by a pulse width modulated signal of 2 MHz and 0.5 MHz, respectively. The interface includes a continuously operating offset compensation approach, which overcomes not only the strong variations due to the large process tolerances of the GaN technology, but also offset drifts due to temperature variations. An accurate pulse width modulated signal with a large duty cycle variation in both channels was achieved. The isolation interface adopts a 6-V power supply, which delivers a quiescent current of 6.3 mA and 7.5 mA to the driver and power control channels, respectively, assuming a signal with a duty cycle of 50%.

A bulk-driven operational transconductance amplifier (OTA) suitable for ultralow-power and ultralow-voltage applications is described. The amplifier exploits local positive feedback in the first stage to increase its transconductance. The OTA entails a single Miller capacitor for frequency compensation, thus saving area occupation and improving frequency performance. As a distinctive feature of the proposed solution, the OTA is stable for capacitive loads higher than 5 pF. Implemented in a 65-nm standard CMOS technology, the proposed solution occupies an area of 10.6$\cdot$10$^{-3}$mm$^{2}$and is powered from 0.3 V, with a total quiescent current equal to 8.5$\mu $A. Experimental measurements show a gain–bandwidth (GBW) product of 1.65 MHz (0.81 MHz) with a phase margin (PM) equal to 70$^{\circ}$(71$^{\circ})$when driving a 50-pF (150-pF) load, featuring the best figures of merit compared to other multistage sub-1-V OTAs in the literature.

This paper presents a frequency compensation scheme of a full GaN operational amplifier for smart power applications. The amplifier is based on a previous topology originally developed for nMOS technology and here adapted for a modern GaN process. The solution is able to drive a capacitive load as high as 1 nF and a suitable design strategy has been developed. The operational amplifier exhibits a very high nominal DC gain of about 135 dB, a unity-gain bandwidth of about 560 kHz with 60° phase margin, a slew rate of about 0.83 V/$\mu$s and a nominal quiescent current consumption of 200 $\mu$A from a 6-V supply.

This study proposes a low-quiescent current two-input/output buffer amplifier for LCD applications. A current reuse technique is employed in the output stage of the buffer amplifier to reduce the quiescent current consumption. An experimental prototype 6-bit LCD column driver with the proposed buffer amplifiers implemented in a 0.35-μm CMOS technology demonstrates that an average value of 0.6 μA static current is consumed in one channel driver. The settling time to settle within 0.2% of the final voltage is 6 μs under a 30-KΩ-resistance and 30-pF-capacitance load. The area of this two-input/output buffer amplifier is 21.5 μm × 190 μm.

We demonstrated the feasibility of the adaptive frequency compensation approach to design maximum- and constant-bandwidth feedback amplifiers. A basic CMOS amplifier exhibiting 66-dB dc gain and 310-MHz gain-bandwidth product was designed. For closed-loop gains ranging from 1 to 10, the closed loop bandwidth was found never lower than 401 MHz. A similar amplifier with equal gain-bandwidth product, but adopting the traditional fixed compensation approach, would exhibit a closed-loop bandwidth decreased to 33 MHz when the gain magnitude is set to 10. The enhanced frequency performance is obtained with a 48% increase in current consumption, while the other main opamp performance parameters remain almost unchanged compared to the standard solution.

The main drawback of current-mode interface circuits for on-chip capacitive sensors is that the measurement sensitivity is adversely affected by the sensor parasitic capacitance. This causes a strong limitation in the range of applicability of CM interfaces. In this paper we propose a technique that avoids this problem and allows the design of high-performance CMOS interfaces. The proposed solution is based on a feedback loop that, during an autotuning phase, sets the driving current level, hence ensuring virtually the same accuracy irrespectively of the parasitic capacitance. The technique was implemented and designed using a 65-nm CMOS technology. Simulation results are found in close agreement with those theoretically expected, resulting also in an increased accuracy of the capacitive variation detection.

We describe an active circuit that can be used as a low-voltage bypass element and that can profitably replace the Schottky diodes in photovoltaic (PV) panels. The proposed solution is made up of a power MOS device with its embedded driving circuitry. The whole circuit does not require a dedicated DC power and is fully compatible with standard CMOS technologies. A prototype is fabricated and experimentally characterized. Compared to conventional Schottky diodes the power dissipation is reduced by more than 70%. Due to its simplicity, the solution can be integrated even directly on the panel.

The present paper addresses an improved and compact low-power high-speed buffer amplifier topology for large size liquid crystal display drivers. The proposed buffer achieves fast driving performance, draws a low quiescent current and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing and settling capabilities by realizing a dual-path push-pull operation of the output stage. No additional bias network is required to fix the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself without auxiliary power dissipation. Simulation results demonstrate that the suggested buffer can drive a 1000-pF column line capacitive load with a 5.8-V/μs slew-rate and a 0.75-μs settling time, while drawing only 3-μA quiescent current from a 3-V power supply.

In this paper the reversed nested Miller compensation (RNMC) approach is reviewed and its design equations are presented. After introducing two new compensation techniques, a coherent and comprehensive comparison of the available solutions is performed by means of a figure of merit expressing the trade-off among gain-bandwidth product, load capacitance and total transconductance, for equal values of phase margin. The proposed comparison outlines useful design guidelines for the optimization of the overall amplifier performance. Simulations proving the effectiveness of the suggested design methodology and analytical comparison are included, showing the substantial advantage of one of the proposed solutions.

This paper addresses a new compact low-power class-B buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by exploiting two current comparators embodied in the input stage, which sense the input signal transients to turn on the output stage transistors. A rail-to-rail stacked mirror differential amplifier is used to amplify the input signal difference and supply the bias voltages for the output stage. Simulation results show that the proposed buffer can drive a 1-nF column line load within 1.8-μs settling time under a full voltage swing, while drawing only 3.5-μA static current from a 3-V power supply.

This work addresses a new compact low-power highspeed output buffer amplifier topology for large-size LCD applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities by exploiting the push-pull output sections of two basic complementary-type input amplifiers to realize a dual-path push-pull operation of the output stage. An auxiliary bias network integrated in the input differential stage allows the quiescent conditions of the class-AB output stage to be inherently controlled without additional power dissipation. Post-layout results confirm that the proposed amplifier can drive a 1-nF capacitive load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current.

A cascode current mirror with auxiliary body-driven feedback loop is proposed. Main performance parameters are analytically evaluated and compared to those of a conventional high-swing cascode and of a recently-proposed body-driven topology. Simulations are also provided confirming improvements in the achievable output resistance (important for short channel technologies), DC accuracy, and input dynamic range. Linearity, bandwidth, noise and voltage requirements are substantially the same of the conventional high-swing cascode solution.

This paper proposes and develops two simple efficient techniques for optimizing the closed-loop transient response of three-stage amplifiers for large capacitive load applications. The proposed approaches exploit a current comparator in the inner amplifier nodes to sense the input voltage transients and switch on an auxiliary driving device providing slew-rate enhancement and settling time improvement without extra static power dissipation. SPECTRE simulations are carried out on a three-stage amplifier adopting a recently proposed RNMC strategy with a voltage follower and two resistors. Simulation results confirm the effectiveness of both proposed techniques, showing a symmetrical step-response with a significant improvement in large-signal speed performance. Both discussed solutions are suitable for any particular three-stage amplifier topology and are also independent of the adopted compensation network.

This paper proposes and develops an original power-efficient reversed nested Miller compensation technique for low-power three-stage amplifiers driving large capacitive loads. The proposed approach exploits dual-active buffers in the compensation network, along with a feedforward gain stage providing enhanced speed performance. A well-defined design procedure for the compensation elements is also developed using the loop-gain phase margin as the main design parameter. To confirm the effectiveness of the proposed technique, SPECTRE simulations on a three-stage amplifier driving a 1-nF capacitive load are carried out adopting the model parameters of a standard 0.35 mum CMOS technology. Simulation results are finally found to be in excellent agreement with the theoretical analysis, showing a considerable improvement of the proposed strategy over other traditional solutions in terms of small-signal and large-signal performance.

A CMOS differential amplifier cell for minimum supply requirements is presented. The solution uses transistors in strong inversion and an original biasing scheme that exploits the bulk terminals of the transistor pair to accurately set the quiescent current and provide common-mode control. As a result, we avoid the use of the tail current source adopted in traditional differential stages. An implementation based on an auxiliary switched-capacitor network used in the feedback control loop is proposed and theoretically examined. Measurements on a prototype fabricated in a standard 0.35- mum technology (with threshold voltages around 0.5 V) and powered with 1.2 V show an error in the bias current of about 15% with respect to the expected value. It was found that the obtained overall performance is comparable to that of a traditional long-tailed differential pair that uses a higher supply of 1.5 V.

We present a flexible mixed-signal architecture for the synthesis of an n-port analog network. It exploits a field programmable gate array as digital processing element and second generation current conveyors as analog input/output blocks. To validate the approach, a prototype is realized for the basic case of a two-port network and experimental results in agreement with those expected are provided.

A novel design-oriented approach for Miller compensation exploiting current buffer/amplifiers is described. The analysis enables a simple design procedure to be outlined, which is in turn applied to a two-stage CMOS OTA driving a large capacitive load. Assuming a 100-pF load, three example compensation networks were designed using alternatively a compensation capacitor as low as 1.3 pF, 0.6 pF and 250 fF. Simulations in very good agreement with theoretical results are also given.

We propose a linearization technique, for CMOS differential pairs employing resistive source degeneration, which exploits the bulks of the pair as additional control terminals. Simulations were performed using a 0.25-μm process, on an example design powered with 2.5V and 1 mA. Compared to the traditional source-degenerated transconductor, the proposed approach allows a THD reduction in the voltage-to-current conversion by 10dB, for an input differential signal of 0.5Vppand for frequencies up to 100MHz.

A CMOS high-linearity transconductor useful for IC filtering applications is presented. It is based on a feedback unity-gain amplifier driving a resistor to achieve linear voltage-to-current conversion. Simulation results are provided on a design example using a 0.35-mum technology, powered from a 3.3V supply, and using a total dc current of 150 muA. The 3-dB bandwidth was 630 MHz and HD3, onto a load resistor of 20kOmega, was -82 dB at 1MHz.

A novel frequency compensation technique for three-stage amplifiers is introduced. Compared to the traditional reversed nested Miller compensation strategy, the proposed one exploits two active stages already included in the amplifier topology, thus no extra circuitry for its implementation is needed. The technique allows to remove the right-half-plane zero and generates a left-half-plane zero, improving the phase margin. Design equations using the phase margin as design parameter are carried out. The proposed technique is used to design, using a standard CMOS 0.35-mum technology, a 2-V three-stage amplifier driving a 500-pF load. The amplifier dissipates 0.24 mW at DC and achieves a 1.75-MHz gain-bandwidth product

We propose an inverting closed-loop amplifier architecture providing high input impedance and a theoretically zero gain error, without requiring infinitely large loop gain. The architecture is based on two nested amplifiers closed in feedback through a resistive network. A straightforward CMOS implementation is also given. Simulations using a 0.35-mum CMOS process are found in agreement with expected results. Monte Carlo simulations have also shown the robustness of the proposed approach against process tolerances

A simple technique to evaluate the linearity performance of a tunnel diode oscillator is presented. The approach is based on the phasor method and avoids redundant computations and/or iterations required by traditionally adopted mathematical tools. Equations found are simply derived, extend our knowledge on harmonics generation and are particularly useful for the designer. A design example is provided and simulations are found in good agreement with expected results

This paper presents a general architecture for an analog-to-digital (A/D) fuzzy converter which performs the A/D conversion and the fuzzification operation on the same functional block, through a programmable membership function. The solution uses as main blocks an A/D converter, a comparator, and some logic inverters and switches. It is characterized by good flexibility and programmability and, compared to conventional approaches, allows a significant amount of silicon area to be saved. The architecture proposed does not depend on the specific A/D converter adopted. However, low-voltage operation and reduced power dissipation as well as full compatibility with digital technologies can be achieved through the use of current-mode design techniques. A CMOS implementation is then proposed and nonidealities, limiting the resolution, are analytically evaluated in detail. Simulations based on a 0.35-/spl mu/m standard technology, which are in excellent agreement with the theoretical results, are also given.

A CMOS voltage to current converter is proposed which is based on a cross-coupled class AB topology. Thanks to its high-linearity and high-frequency performance, the circuit can be used in high-frequency applications such as mixers, IF amplifiers and filters, etc., where linearity is one of the most critical performance parameters. When the proposed circuit is compared with other voltage to current converters such as the source-coupled pair a much higher linearity is achieved at the same power consumption.

The authors present a CMOS class AB current mirror which adopts an innovative dynamic biasing approach. Due to it, a minimum power supply is required which is given by one threshold voltage plus two saturation voltages. The excellent performance of the circuit is confirmed by simulations on a design example implemented in a standard 0.8 /spl mu/m CMOS technology. The circuit uses a 1.2 V supply and the threshold voltages of transistors are around 0.8 V.

A high-accuracy high-speed current comparator is presented which has well-controlled input resistance and bias currents. Moreover, compared to previous high-speed solutions, it has an accuracy five times better with a lower power consumption.>