VLDB 2026 Research / reviewers in the wild / expert
Atsushi Matsuo
dblp:63/6991
· DBLP profile ↗
6ranked-venue papers
4as first author
2since 2021 · last 2021
0000-0003-1071-2696ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author · 1 since 2021Theory of computation · 2 · 2 first-author · 1 since 2021Applied, interdisciplinary, general and emerging computing · 2 · 2 first-author · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor ArchitecturesabstractWe usually use Mixed-Polarity Multiple-Control Toffoli (MPMCT) gates to realize large control logic functions for quantum computation. A logic circuit consisting of MPMCT gates needs to be mapped to a quantum computing device that has some physical limitation; (1) we need to decompose MPMCT gates into one or two-qubit gates, and then (2) we need to insert SWAP gates such that all the gates can be performed on Nearest Neighbor Architectures (NNAs). Up to date, the above two processes have been independently studied intensively. This paper points out that we can decrease the total number of the gates in a circuit if the above two processes are considered dynamically as a single step; we propose a method to inserts SWAP gates while decomposing MPMCT gates unlike most of the existing methods. Our additional idea is to consider the effect on the latter part of a circuit carefully by considering the qubit layout when composing an MPMCT gate. We show some experimental results to confirm the effectiveness of our method. Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita |
ASP-DAC | 1 |
| 2021 | Variational Quantum Eigensolver and Its Applications
Atsushi Matsuo |
RC | 1 |
| 2020 | Optimization of quantum circuit mapping using gate transformation and commutation
Toshinari Itoko, Raymond H. Putra, Takashi Imamichi, Atsushi Matsuo |
Integr. | 4 |
| 2019 | Quantum circuit compilers using gate commutation rulesabstractThe use of noisy intermediate-scale quantum computers (NISQCs), which consist of dozens of noisy qubits with limited coupling constraints, has been increasing. A circuit compiler, which transforms an input circuit into an equivalent output circuit conforming the coupling constraints with as few additional gates as possible, is essential for running applications on NISQCs. We propose a formulation and two algorithms exploiting gate commutation rules to obtain a better circuit compiler. Toshinari Itoko, Raymond H. Putra, Takashi Imamichi, Atsushi Matsuo, Andrew W. Cross |
ASP-DAC | 4 |
| 2019 | Reducing the Overhead of Mapping Quantum Circuits to IBM Q SystemabstractWe propose an efficient approach to optimize the number of necessary SWAP gates when we perform a quantum circuit on IBM Q system. Our idea is to change the order of quantum gates (if possible) so that each sub-circuit has only gates performing on adjacent qubits. For each sub-circuit, we utilize a SAT solver to find the best qubit placement such that the subcircuit has only gates on adjacent qubits. Each sub-circuit may have a different qubit placement such that we do not need SWAP gates for the sub-circuit. Thus, we insert SWAP gates between two sub-circuits to change the qubit placement which is desirable for the following sub-circuit. To reduce the number of such SWAP gates between two sub-circuits, we utilize A* algorithm. Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita |
ISCAS | 1 |
| 2019 | An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid
Atsushi Matsuo, Shigeru Yamashita |
RC | 1 |