Current embedded systems are increasingly using networks, be it for connecting different components or in form of Network on Chips in case of Multi-Processor System on Chip. Knowing the performance parameters of those networks, especially in case that parts of the network are damaged, is the key to allow reliable behavior of the system. In this paper, we present an approach for measuring the performance parameters of embedded networks under different load and fault scenarios. First, the performance parameters of the network are measured in the nominal case. This information is then used to create a model of the network. For this model we provide a simulation environment, which injects faults into the network to evaluate the network under failure scenarios. We evaluated our approach on a Network on Chip consisting of 16 nodes arranged in a 4×4 matrix. Our evaluation shows that our approach can evaluate the fault effects in the network with good quality.

Several approaches exist for specification mining of hardware designs, both at the RTL and system levels (e.g, TLM). These approaches mine assertions that specify the behavior of the design. Some of the techniques require the source code itself while others can extract assertions directly from simulation traces. The performance of some approaches is highly dependent on the number of simulation traces/use cases while there exist approaches which can extract assertions from a limited number of simulation traces. Apart from this aspect, the core of each assertion miner is different from the other ones. Some use expression templates to define assertions while some are based on the static analysis or information flow analysis. Unfortunately, it has been rarely considered which of the current approaches are more effective in describing functionality of particular types of designs. Thus, in this work, we analyze assertion miners which are template based and dynamic dependency graph based, respectively. We generate assertions from both approaches. The evaluation considers fault analysis on both assertion sets of extracted assertions. Moreover, both sets are combined and fault analysis has been applied on them. Experimental results show that each set approximately detects the same number of faults while when the two sets are combined the number of detected faults increases. Finally, a new, more efficient architecture for an effective assertion miner has been developed based on the study in this work.

We present a technique to automatically generate System Verilog-Assertions from designs using dynamic dependency graphs. We extract relations between signals of the design using only a few simulation runs, which drastically reduces the required number of use cases compared to other approaches. Additionally, unlike previous approaches, we do not use expression templates to establish those relations. We abstract from the concrete use cases by inserting symbolic values and by merging similar conditions in time. A model-checker verifies the correctness of the generated properties. The evaluation shows that our approach is able to create more expressive properties than state of the art techniques, while requiring less simulation data.

CPS, that consist of a cyber part – a computing system – and a physical part – the system in the physical environment – as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment. This paper provides an overview of techniques discussed in the special session to tackle these challenges throughout the stack of layers of the computing system while tightly coupling the design methodology to the physical requirements.

In modern chip design, many different blocks are assembled in a single chip. Normally, these blocks have been written by different developers or even licensed from other companies. Correctly connecting all blocks is a tedious task. State of the art tools for automatically generating the connections either require identical port-names or additional user input describing the intended connections.

SUMMARY Many modern automated test generators are based on either metaheuristic search techniques or use constraint solvers. Both approaches have their advantages, but they also have specific drawbacks: Search‐based methods may get stuck in local optima and degrade when the search landscape offers no guidance; constraint‐based approaches, on the other hand, can only handle certain domains efficiently. This paper describes a method that integrates both techniques and delivers the best of both worlds. On a high‐level view, the proposed method uses a genetic algorithm to generate tests, but the twist is that during evolution, a constraint solver is used to ensure that mutated offspring efficiently explores different control flow. Experiments on 20 case study programmes show that on average the combination improves branch coverage by 28% over search‐based techniques while reducing the number of tests by 55%, and improves coverage by 13% over constraint‐based techniques while reducing the number of tests by 73%. Copyright © 2013 John Wiley & Sons, Ltd.

The complexity of modern chips is rapidly increasing. To fulfill tight time-to-market constraints, more and more blocks from previous designs are reused or third party IP blocks are licensed. However, such blocks are often only poorly documented making adjustments to the blocks a difficult task. This paper presents a technique for automatic feature localization for hardware designs. Our approach helps a developer in understanding a design by localizing parts of the code which implement a certain feature of interest. We evaluate the approach on three open source designs. For those designs, our approach yields a more precise localization of the code implementing the different features than the documentation of the design.

Modern chip designs are getting more and more complex. To fulfill tight time-to-market constraints, third-party blocks and parts from previous designs are reused. However, these are often poorly documented, making it hard for a designer to understand the code. Therefore, automatic approaches are required which extract information about the design and support developers in understanding the design. In this paper we introduce a new dynamic data flow analysis tuned to automate design understanding. We present the use of the approach for feature localization and for understanding the design's data flow. In the evaluation, our analysis improves feature localization by reducing the uncertainty by 41% to 98% compared to a previous approach using coverage metrics.

Due to the increasing complexity modern System on Chip designs are developed by large design teams. In addition, existing design blocks are re-used such that the knowledge about these parts of the design entirely depends on the quality of the documentation. For a single designer it is almost impossible to have detailed knowledge about all blocks and their interaction.

Many modern automated test generators are based on either meta-heuristic search techniques or use constraint solvers. Both approaches have their advantages, but they also have specific drawbacks: Search-based methods get stuck in local optima and degrade when the search landscape offers no guidance; constraint-based approaches, on the other hand, can only handle certain domains efficiently. In this paper we describe a method that integrates both techniques and delivers the best of both worlds. On a high-level view, our method uses a genetic algorithm to generate tests, but the twist is that during evolution a constraint solver is used to ensure that mutated offspring efficiently explores different control flow. Experiments on 20 case study examples show that on average the combination improves branch coverage by 28% over search-based techniques and by 13% over constraint-based techniques.