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Kiyo Ishii

dblp:63/9559 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2017
0000-0002-0226-577XORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 77% Hardware reliability and fault tolerance · 23%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip
optical interconnection networks
0.312017
High-Bandwidth Low-Latency Approximate Interconnection Networks · HPCA 2017
Hardware reliability and fault tolerance › soft errors
soft error resilience
0.112017
High-Bandwidth Low-Latency Approximate Interconnection Networks · HPCA 2017

Methods — techniques the papers use, named apart from their topics

symbol mapping coding · 0.3quadrature amplitude modulation · 0.3
YearPublicationVenuePosition
2017 High-Bandwidth Low-Latency Approximate Interconnection Networks
abstract
Computational applications are subject to various kinds of numerical errors, ranging from deterministic roundoff errors to soft errors caused by non-deterministic bit flips, which do not lead to application failure but corrupt application results. Non-deterministic bit flips are typically mitigated in hardware using various error correcting codes (ECC). But in practice, due to performance and cost concerns, these techniques do not guarantee error-free execution. On large-scale computing platforms, soft errors occur with non-negligible probability in RAM and on the CPU, and it has become clear that applications must tolerate them. For some applications, this tolerance is intrinsic as result quality can remain acceptable even in the presence of soft errors (e.g., data analysis applications, multimedia applications). Tolerance can also be built into the application, resolving data corruptions in software during application execution. By contrast, today's optical networks hold on to a rigid error-free standard, which imposes limits on network performance scalability. In this work we propose high-bandwidth, low-latency approximate networks with the following three features: (1) Optical links that exploit multi-level quadrature amplitude modulation (QAM) for achieving high bandwidth; (2) Avoidance of forward error correction (FEC), which makes optical link error-prone but affords lower latency; and (3) The use of symbol mapping coding between bit sequence and QAM to ensure data integrity that is sufficient for practical soft-error-tolerant applications. Discrete-event simulation results for application benchmarks show that approx networks achieve speedups up to 2.94 when compared to conventional networks.
Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi
HPCA2
2016 Distributed-like optical path switch control approach for interconnect networks
abstract
A new approach for optical path switch interconnect network is proposed. In the proposed network, optical switches are controlled locally without communications with a centralized controller, which offers high affinity with existing packet-based interconnect networks.
Kiyo Ishii, Shu Namiki
HPSR1
2016 Toward exa-scale photonic switch system for the future datacenter (invited paper)
abstract
This paper reviews various optical switch technologies, then discusses how to realize an optical circuit switching interconnect capable of more than 10 Tbps link bandwidth and more than 100,000 end points scalability for data centers or high performance computers. Introducing the wavelength division multiplexing transmission technology and a simple distributed-like control scheme of optical switches is proposed, with the associated challenges discussed.
Kiyo Ishii, Shu Namiki
NOCS1