The recent trends for nanoelectronic computing systems include machine-to-machine communication in the era of Internet-of-Things (IoT) and autonomous systems, complex safety-critical applications, extreme miniaturization of implementation technologies and intensive interaction with the physical world. These set tough requirements on mutually dependent extra-functional design aspects. The H2020 MSCAITN project RESCUE is focused on key challenges for reliability, security and quality, as well as related electronic design automation tools and methodologies. The objectives include both research advancements and cross-sectoral training of a new generation of interdisciplinary researchers. Notable interdisciplinary collaborative research results for the first halfperiod include novel approaches for test generation, soft-error and transient faults vulnerability analysis, cross-layer fault-tolerance and error-resilience, functional safety validation, reliability assessment and run-time management, HW security enhancement and initial implementation of these into holistic EDA tools.

Adaptivity to changing demands is a key feature of many systems in computationally challenging applications. This feature achieved with reconfigurable hardware, providing a good balance between implementation efficiency and flexibility. However, for some areas the specification may also include a high level of system dependability. In particular, FPGA-based implementations may be used in systems that require long-time dependable operation over several years. This paper presents a new approach for online self-detecting and handling permanent faults in the field programmable gate array (FPGA) based soft processors with the lowest overhead in time and area. The method presented includes both the fine-grain diagnosis of faults in an FPGA and a technique for repair by re-configuration at the lowest cost. The results were achieved using Xilinx FPGAs based on the 28 nm technology and two soft processors.

Wireless signal transmission has become the essential core of modern communication systems. Forward error correction (FEC) has a critical role in securing quality and reliability. FEC circuitry, implemented in nano-technologies, may suffer from transient and permanent fault effects such as radiation-induced single event upsets (SEUs) and aging effects. Such circuits may actually mask non-permanent hardware faults, but possibly at the expense of transmission error correction. Single error correction (SEC)-double error detection (DED) methods are favorably used for rapid error correction within a single clock cycle, and they may even be used for multiple error correction in iterative approaches. But such schemes fail in case hardware faults and transmission faults combine. Where FEC circuits are used in systems that need to be highly dependable over a long life time or which may have limited access for repair, the option of built-in self repair (BISR) may become a must.

Communication technologies have experienced an explosive development. Various short-distance communication systems have been used as a way of connecting embedded electronic systems in industrial applications. Test- and error detection or correction technologies have to meet new timing challenges and requirements in modern real-time and safety-critical systems, also set by Industry 4.0. Encoders using generator polynomials with linear-feedback shift registers (LFSRs) are the key parts of communication technologies, widely used in most of today's integrated as well as field systems. This paper presents a comparison of three basic ways of implementation of adaptive encoders configurable LFSRs using conventional configurable solutions, reconfigurable LUTs in SLICEMs in Xilinx FPGAs, and also encoders using standard Xilinx partial reconfiguration.

Due to the downscaling of transistor feature sizes, nowadays integrated circuits are more vulnerable to various effects that can cause faults during operation. Appropriate mechanisms for handling these faults in the field are required to meet certain dependability demands nonetheless. At the same time, the overhead in chip area and power consumption that is caused by such fault tolerance techniques needs to be reasonable. This calls for a dependability aware design space exploration which carefully evaluates the costs and benefits of various fault tolerant implementations of the system. This paper first introduces a tool that supports this design space exploration for hardware redundancy based fault tolerance. Among other features, it offers very fast overhead estimations for the supported set of fault tolerance techniques. The paper describes in detail how the estimations of the power overhead are performed. The accuracy of these estimations is evaluated by comparison with power analysis results obtained by a commercial EDA tool.

In state-of-the-art automotive controllers, functional tests are used to check their integrity in the field. Features dedicated to production test of integrated circuits such as scan-chains are not applied in the embedded system. However, such test structures enable a more effective and diagnostic test, which improves the fault analysis in case of a system failure and even increases system reliability. To archive this, an access to the integrated test logic is required. In this paper, we describe a concept of a test access to embedded systems via high-speed standard interfaces. The extended test logic as well as an appropriate test routine are presented.

The downscaling of transistor feature sizes has led to integrated circuits that are more susceptible to various fault effects. In order to meet dependability requirements, appropriate fault tolerance techniques have to be applied. This adds another challenging task to the design process of integrated circuits, which has to include a careful evaluation of costs and benefits of different fault-tolerant implementations. This paper presents a tool that supports this design space exploration by automatically evaluating the use of hardware redundancy-based fault tolerance for circuits specified in structural VHDL. The tool's main features as well as its integration in established EDA flows are described.

The on-going down-scaling of devices in microelectronics has resulted both in reliability problems and in problems regarding power dissipation. Even worse, reducing supply voltages below 1 V has resulted in problems due to inevitable parameter variations from production on one side and from parameter shifts by aging effects on the other hand. So far, much work has been invested in new methods of fault-tolerant computing using code based error detection and -- correction or triple modular redundancy (TMR) at substantial extra cost in hardware and power. On the other hand, there has been a line of development to handle parameter variations by selectively correcting delay faults in order to achieve stable circuit operation and supply voltages down to 0.6V or below. The Razor and Bubble Razor architectures developed for such purpose may even handle short transient faults. However, they are acceptable in terms of overhead only if applied to a small share of signals that suffer from critical paths in combinational logic. What is missing is an architecture that can handle such path delays and transient fault effects at reasonable cost, optionally in combination with methods that allow for the detection and compensation of permanent faults also. The paper presented here shows an effort in this direction and estimates cost and overhead.

This paper proposes a new approach on designing application specific instruction set processors (ASIP). The design process is driven by a step by step refinement of intermediate codes, known from compiler backends. In every step the intermediate code can be simulated, and profiled. Based on profiling information it can be further transformed to an optimized or refined intermediate code. The whole transformation process is implemented in a GUI-based design tool, named CoMet, whose main component is a configurable simulator for intermediate codes. It will be shown how the configurable intermediate code simulator is used, and how the intermediate code transformation and the generation of a VHDL of the ASIP model will work in the CoMet tool.

Large-scale integrated circuits and systems fabricated in nano-technologies exhibit new and enhanced fault properties which limit both their reliability and their life time. Transient fault effects have found most attention so far. They must be handled by on-line check and fault compensation based on duplication and triplication, typically at a significant amount of extra power. Such techniques are not suitable for life time extension, since their redundant elements all undergo wear-out effects in hot operation. Repair technologies that perform a process of system re-organization and introduction of cold redundancy may extend system life time, but they are too slow to catch and correct transient and permanent fault effects in hot operation. The essential task therefore remains to find methods and architectures that will provide on-line check in combination with self repair techniques at a minimum cost in extra power.

Reconfigurable architectures are increasingly employed in a large range of embedded applications, mainly due to their ability to provide high performance and high flexibility, combined with the possibility to be tuned according to the specific task they address. Reconfigurable systems are today used in several application areas, and are also suitable for systems employed in safety-critical environments. The actual development trend in this area is focused on the usage of the reconfigurable features to improve the fault tolerance and the self-test and the self-repair capabilities of the considered systems. The state-of-the-art of the reconfigurable systems is today represented by Very Long Instruction Word (VLIW) processors and reconfigurable systems based on partially reconfigurable SRAM-based FPGAs. In this paper, we present an overview and accurate analysis of these two type of reconfigurable systems. The content of the paper is focused on analyzing design features, fail-safe and reconfigurable features oriented to self-adaptive mitigation and redundancy approaches applied during the design phase. Experimental results reporting a clear status of the test data and fault tolerance robustness are detailed and commented.

Recently some fine-grained self-repair techniques for processors have been published that can handle permanent faults in particular components of a processor in-the-field. Unfortunately, the generation of diagnostic tests that can be used in-the-field for fault localization in these components is not solved satisfactorily. A few papers paid attention on improving the diagnostic capabilities of software-based self-test programs, but with emphasis on manufacturing test. This paper presents a systematic approach for the generation of test programs for diagnostic tests in-the-field. Moreover, the test program is generated in such a way that it specifically targets for faults that can be handled with an available self-repair method. The functional test programs are constructed from test patterns that can be generated with standard ATPG tools. The results show that diagnostic test programs will have an overhead in test program length ranging from 0% to 391% compared with non-diagnostic test programs.

Digital integrated circuits fabricated in nano-technologies have first shown to be more vulnerable to transient errors effects than their predecessors. But they also show effects of stress-induced defects resulting in early life-time failures. In general, power dissipation problems and dielectric stress, due to high field strength, are the main reasons for shortened life-time expectations. On the other hand, system designers require highly reliable and long-time dependable hardware, for example in automotive applications. On-line error detection and-compensation using either codes or, in the more general case, double or triple modular redundancy (DMR and TMR), has been used for decades, but causes higher power dissipation in nano-logic, additional stress, and is therefore no cure in terms of life-time extension. Savings on hardware and power are possible, if resources can be re-allocated to produce local TMR upon demand. However, such techniques may cause sudden signal delays after the detection of errors, which are not easy to handle in synchronous systems. The paper makes an analysis of problems and shows first results in architectures for fast and efficient error detection and correction.

Integrated circuits and systems implemented by using nano-technologies show a combination of known and new faults effects, which affect their reliability and their operational life time, specifically in safety-critical applications. Transient fault effects such as single and multiple event upsets (SEUs and MEUs) require fast error detection and compensation. Permanent faults may occur due to early life time failures on one side and stress-induced rapid aging on the other hand. They need to be compensated by repair technologies, preferably using “fresh” resources for the replacement of faulty functional units. As self repair is typically not a fast process and requires extra time while the system is off-line, on-line fault compensation must also catch and handle permanent faults that occur during “hot” operation. If on-line-test and error compensation on one side and repair technologies on the other hand are implemented independently, the resulting overhead in redundant circuitry becomes prohibitively high. In the following paper we therefore introduce a new concept of logic design which can meet the essential demands at reasonable cost using a flexible allocation of redundancy.

This paper presents performance estimations for a scalable VLIW soft-core in various XILINX FPGAs. It covers the low-cost low-power devices as well as the latest high-end FPGA families. The results represent the maximal clock frequency of the complete design including the processor core and the code and data memories. A scaling test has been done as well. In this case, the VLIW soft-core has incorporated various numbers of execution units and issue slots. It shows that the clock rate of the core scales much better with the number of execution units than proposed in estimations for standard-cell-based designs. It does not always create a lower clock rate of the design. Moreover, the highest possible clock rate shows some unexpected behaviour, when scaling the number of execution units. In some cases, a higher number of execution units cause no clock rate penalty. Finally, both ways of scaling the performance are compared with each other and some conclusions for a design space exploration of soft-cores are presented.

Nano-electronic circuits and systems with a minimum feature size of 45 nm and below exhibit an increasing variety of defect and fault mechanisms. Their rising sensitivity to radiation and coupling induced single and multiple event upsets is one problem, new or enhanced aging processes that lead to early lifetime failures (ELF) pose another threat. The compensation of transient fault effects is a well explored area of science, while repair technologies that tackle permanent faults have so far found a broad acceptance only for embedded memories and for FPGA-based systems. In this paper we describe two alternative schemes of fault detection and on-line error correction based on virtual and time-shared triple modular redundancy (TMR). Optionally, both schemes allow for optional built- in self repair at reasonable total cost.

We present a novel concept for handling permanent faults in a statically scheduled heterogeneous multi-core system by means of a software-based self-reconfiguration. Hard faults are handled in a hierarchical cross layer manner, either locally by each core itself, or globally by reconfiguring the full system. Local reconfiguration of a defect core is based on the adaptation of the executed task to the current fault state of the core, such that defect components are never used. This adaptation is achieved by a rescheduling of the program code of the task. If this local reconfiguration fails, then the binding of tasks to cores is modified. Because heterogeneous cores are allowed, this may require a rescheduling of the tasks whose binding is changed. Estimations for the runtime of such a global reconfiguration are presented. Moreover, it is shown that systems that support the global reconfiguration achieve the same fault tolerance level as systems with local repair only, but with reduced hardware overhead.

In recent years many authors have addressed the growing vulnerability of nano-electronic circuits and systems to transient faults and wear-out effects. Hence present and even more future electronic systems need the property of resilience against different types of fault effects for long-term dependable operation. Fault detection, error compensation, and also repair technologies require a substantial overhead in extra hardware resources, which add to system size, cost and power consumption. In this paper we present a first attempt to combine resources for transient fault handling and for permanent fault repair in a unified approach.

The localization of permanent faults in a processor is a precondition for applying (self-)repair functions to that processor core. This paper presents a software-based self-test technique that can be used in the field for test and fault localization, there-by providing a high diagnostic resolution. It is shown how the self-test routine is adapted in the field to already detected faults in the processor, such that these faults do not affect the test- and diagnostic capability of the self-test routine. By this it becomes reasonable to localize multiple permanent faults in the processor. The proposed self-test is software-based, but it requires a few modifications of the processor. The feasibility of the technique is presented by an example; limitations are discussed, too.

In state-of-the-art automotive controllers, test in the field cannot use features dedicated to production test. However, the enhanced testability by access to features such as scan-chains can increase the effectivity and the diagnostic features of tests in the field significantly. Therefore, an appropriate test access to the integrated test-technology is required. In this paper, we describe the possibilities and limitations of in-field access to embedded scan-test via high-speed standard interfaces. By use of such common interfaces for the test of integrated circuits, it should be possible to run test routines, e.g. for a complete automotive control unit, which includes functional tests as well as structure-oriented tests, in the field.

The continued scaling of microelectronic elements down to atomic dimensions has a growing negative influence on their reliability and lifetime. Countermeasures like self repair and destressing are able to slow down this development, whereby a combination of these approaches promises even better results. This paper describes an extension of a M-of-N-systems with activity migration by load balancing and especially the for this purpose implemented control logic. These extensions enable the workload to be fairly distributed over all fault free functional units, even if one to all redundant units fail and without interaction of the user. This ensures an even ageing process of the whole system.

Reliability and the mean lifetime are major aspects in today's semiconductor device manufacturing. The continuous downscaling of transistor sizes and power supplies are the root causes of higher vulnerabilities of integrated circuits against time zero process variation, time dependent degradation and random faults induced by environmental influences like particle strikes. Handling permanent faults becomes inevitably a suitable solution to guarantee high reliabilities as well as increased lifetimes. Built-in self-repair is a possible solution, which exchanges faulty units with spare parts at the costs of extra hardware. In this paper, we evaluate the influence of different replacement strategies and their resulting additional hardware structures on reliability and mean lifetime. This analytical process allows to find the optimal replacement strategy for a given system, without implementing and synthesizing each case.

This paper presents a new in-the-field self-test approach for a specific VLIW processor model with emphasis on the diagnostic capability of the test. It is intended to be used as start-up test in-the-field in order to localize permanently defect components in a VLIW processor model, which provides self-repair capability. In order to overcome the drawbacks of several existing self-test techniques, a combination of them in a hierarchical manner is provided. By this, the data path of the VLIW processor can be checked within a very short time and at a fine grained diagnostic level. The results show that the required diagnostic resolution for the used processor model with self-repair capability can be obtained with a relatively small hardware overhead of about 6%.

Technology scaling inevitably leads to fabrication processes, which are more susceptible to production faults. At the same time, devices become more vulnerable to wear-out effects, which reduce the long term system reliability. The upcoming challenge of future designs is the development of integrated test and repair techniques dealing with both types of fault mechanisms. Our paper presents a built-in self-test (BIST) and repair solution for regular data path structures of VLIW processors by software-based self-test (SBST). After fault detection and localization by software a hardware reconfiguration, by using redundant components, takes place. Our software test and repair solution can be used to improve yield as well as reliability.

Reliability issues concerning integrated systems based on nano-electronic devices have been a matter of research for years. Early focus was on transient fault effects due to particle radiation and failing interconnects due to thermal stress and metal migration. More recently, transistor parameter deterioration due to permanent input voltages at MOS transistor gates has been investigated. One potential cure to the problem is extra circuitry that is kept in redundancy for eventual purposes of self-repair. This circuitry, however, may also be used to redistribute activities among several basic blocks for a minimization of stress effects. The paper describes an architecture that can perform de-stressing and self repair in combination and describes costs and limitations.

Test technologies for integrated circuits have traditionally tried to maximise test data compression rates, because these are essential for keeping test time and costs low. However, power consumption during the test process is a problem that has been addressed on recently. Excessive power consumption may result in thermal stress and increased voltage drops within the circuit, which implies increasing signal delays. Thereby even fully-functional circuits may fail during delay testing. Therefore, in this paper a flexible concept is proposed which combines test pattern compression using a scan controller concept and reduction of power consumption during the fast capture cycles of transition delay tests. Essentially, this concept consists of a Greedy algorithm, which fills X-rich pattern with 0s or 1s step-by-step, and an event-driven logic and power consumption simulator, which calculates the costs of these steps. The implemented concept is applied to X-rich test sets of ISCAS'89, ITC'99 benchmarks and OpenSparc cores. Results show a best case with 96 percent test data reduction combined with 32 percent less peak capture power. With this concept it is also possible to reduce the peak power for shift-in, launch and shift-out cycles by over 50 percent.

Technology forecasts concerning the development of CMOS technologies predict a higher level of intermittent faults due to radiation effects, but also a higher density of permanent fault effects due to inevitable parameter shifts and higher stress factors. For high production yield and long-term dependable operation, mechanisms of built-in self repair that can be used after production test and in the field of application are becoming a must. The architecture introduced in this paper includes mechanisms for logic self repair that may also cover local interconnects.

The design space of integrated circuits grows due to the need of fault recognition and error compensation. To meet reliability requirements, several reliability increasing methods have to be evaluated. We present a reliability estimation process which allows estimating the resulting reliability of a modified circuit without the need of synthesis. For further speed up, synthesis results after choosing a reliability increasing methods are analyzed. The process is applied to a case study which proves applicability.

Predictions for the properties of integrated circuits and systems fabricated in emerging nanotechnologies indicate a rising level of static and dynamic faults due to new fault mechanisms. Not only transient faults due to particle radiation are becoming a problem, but also wear-out effects on transistors and interconnects. While transient faults can be covered by well-known technologies such as error-correcting codes and triple modular redundancy, permanent faults essentially need a technology that provides built-in self repair (BISR). BISR is actually known and available for regular structures such as memory blocks, but is much more difficult to implement on irregular logic. The paper proposes a scheme for logic BISR, gives estimates for the associated overhead, and describes inherent limitations.

Fault diagnosis has recently become an important issue in IC production test because of the need to enforce high manufacturing yield. Furthermore, fault diagnosis is a pre-condition for any technology of built-in self repair that may be used in the field of application where long-time dependable systems are necessary. An "embedded" diagnostic self test has to get along with a minimum of memory space and computing power, since it may have to make a system working during a system start-up phase. Using inherent regularity on logic de-signs can simplify diagnostic tests considerably by reducing the amount of reference data significantly.

Built-in self test (BIST) and built-in self repair (BISR) techniques have been developed for memory blocks in recent years. Such techniques are suited to enhance production yield, but also to facilitate long-term dependable circuits though self repair in the field of application. BISR for logic circuits has shown to be much more complex, for which only a few approaches have been published so far. However, the roadmap of semiconductor industries sees a requirement of such technology by about 2012. This paper introduces a basic BISR methodology for logic circuits.

SystemC has been widely accepted for the description of electronic systems. An essential advantage of a SystemC description is the possibility of a built-in compiled-code simulation. Beyond the functional simulation for validation of a hardware design, there are additional requirements for an advanced simulation of faults in order to analyze the system behavior under fault conditions. The paper introduces known and novel methods of SystemC-based simulations with fault injections and provides first results. Some strategies are shown to accelerate the SystemC simulation by parallel computing. Additionally, we present gate level and switch level models for an effective simulation in SystemC.

Physical design for digital ICs, based on standard cells, has long been performed without explicit consideration of timing and power related to interconnects. With delays on wires more and more dominating the delays on logic paths, such design styles are becoming obsolete. What is needed is an iterative inclusion of power and timing aspects into the design flow for placement and routing, which yields economic results without multiple loops in the design flow. Basic problems and solutions in the implementation of such a design flow are presented.

Test technology development for processor-based Systems on a Chip (SoCs) has mainly focused on quality and cost of production test. More recently, test technologies that facilitate self test in the field of application are getting additional attention. Hardware-based built-in self test (BIST) is well understood for logic and for memory block, but can hardly cope with changing test strategies. We present a scalable test architecture based on a configurable test processor and a distributed modular scan controller that facilitates self test for logic and for bus structures and can optionally support externally controlled production test.

In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and -correction logic. We describe an easily portable approach, which can be applied to a wide variety of multi-GHz industrial designs

The ever-increasing complexity of systems on a chip (SoCs) has driven scan-based logic test technologies to their limits. Built-in self-test is one possible solution to overcome the problem. However, externally controlled test procedures that allow the re-use of existing testers and adaption to changing patterns seem to gain a higher level of industrial acceptance. Then a high degree of test pattern compaction without sacrificing test coverage is essential. This paper describes a versatile pattern compaction scheme that is independent from special ATPG tools, can be optimized for either hard-to-test versus large circuits and can even accommodate bit settings in LFSR outputs

Fault simulation technology is essential key not only to the validation of test patterns for ICs and SoCs, but also to the analysis of system behavior under fault transient and intermittent faults. For this purpose, we developed a hierarchical fault simulation environment that uses structural VHDL models at the gate level, but is able to model embedded blocks in C++. With SystemC becoming a de-facto standard in high-level modeling, a simulation approach had to be developed which makes effective use of SystemC technology by encapsulating such "threads" into the fault simulation environment. Furthermore, it can be shown that SystemC allows the modeling of complex transistorlevel structures, for which equivalent gate-level representations are not adequate.

Main stream scan test technology development has focused on a cost-efficient usage of external testers in conjunction with minimized on-chip pattern generators. Alternatively, an on-chip test processor that works with highly compacted test patterns from a ROM device allows a software-based self test procedure in the field of application, e.g. during startup tests. Furthermore, such an approach may facilitate self repair function, if the faulty logic block or gate can be identified. We present first investigations on an "embedded" scan-based fault diagnosis, efforts and limitations

Systems on a chip (SoCs) in safety-critical applications need features such as built-in self-test, on-line self-test and error compensation of transient faults. With ever-shrinking feature size, also built-in self-repair (BISR) may become a must. While BIST and BISR are well understood and frequently implemented for embedded memory blocks, BISR for random logic is by far an unsolved problem. Logic circuits based on field-programmable gate arrays (FPGAs) are a technology base that allows for functional reconfiguration in the field of application. In this paper we investigate on the possibilities and limitations of logic BISR for FPGAs

Systems on a chip (SoCs) that combine several processor cores plus multiple interconnects are becoming a standard in advanced technologies. For such systems, a comprehensive test strategy that combines external test and self test capabilities as well as on-line and off-line test is becoming a must in order to manage fault mechanisms that are expected for deep sub-micron technologies. Recently, we have developed a hierarchical test concept for SoCs that relies on a test processor as a "hard core". This paper describes an advanced test concept that may serve to support off-line self test as well as advanced on-line test, also including fault diagnosis features.

Silicon IC technology is entering a new stage of development with the arrival of structures below 100 nm. Such devices are volatile to external radiation effects caused by radioactive particles. Hence circuits in safety critical applications must be self-testing and self-correcting. Production test for complex ICs in deep sub-micron technology is also becoming impossible without built-in self test technology. In this paper, we try to analyze in how far self-test technology for production test and for online self test can be combined for reducing the overall overhead for testing.

This paper deals with the protection of control signals - the detection and fast correction of soft errors in the global control logic, control signal lines or control signal pipelines of microprocessors. As detection techniques, we compare different duplication and prediction schemes for control logic. We discuss several error correction techniques with respect to their suitability for the correction of control signal errors in high-performance processor architectures. We investigated different rollback methods which work with the re-execution of data path operations with a variable rollback distances or a selective control signal repetition. A complete solution for a distributed control signal observation and recovery (protection) scheme with regards to architectural conditions of high-performance processors is proposed.

This paper introduces a new concept for the self test of systems on a chip (SoCs) with embedded processors. We propose hardware- and software-based test strategy. A minimum sized test processor was designed in order to perform on-chip test functions. Its architecture contains special adopted registers to realize LFSR or MISR functions for pattern de-compaction and pattern filtering. High-performance interfaces allow parallel and serial pattern in and output, and a fast test vector comparison. The architecture is scalable and is based on a standard RISC architecture in order to facilitate the use of standard compilers.

HEARTLESS (Hierarchical Register-Transfer-Level Fault-Simulator for Permanent & Transient Faults) was developed to simulate the behavior of complex sequential designs like processor cores in case of transient and permanent faults. HEARTLESS can be enhanced by propagation over macros described in a C++ function. Available is a C-interface for access to internal signals during the simulation.

Self-test strategies for processors in embedded core-based systems have recently found great attention for two reasons. First, production test for embedded cores is becoming a problem due to inaccessible processor pins. Second, self-test is a very desirable feature for processors in applications that require a high level of dependability over a long life time. Standard processors or processor-cores used in embedded systems are not accessible for a full-scale redesign. Therefore methods must be developed that facilitate self-test by keeping the original cores as unharmed as possible. The approach presented here duplicates only the truly necessary parts of a standard processors for test and back-up purposes including capabilities of on-line self-test. Transient faults are recognized and compensated. In a second step, the back-up processor itself becomes fully self-testing and fault tolerant towards a highly dependable system solution by state-encoding of control paths and Berger code check in the data path.

Combining different techniques for sequential automated test pattern generation (ATPG) can help overcome their respective limits and exploit their advantages. In this paper, a hybrid technique resulting from mixing topologic and symbolic approaches to the sequential ATPG problem is presented. Macros are first identified within the circuit (possibly resorting to RT-level knowledge of circuit architecture). Information about macro behavior is then computed and efficiently stored resorting to symbolic techniques. A topological tool exploits this information during the ATPG process to speed-up the propagation task and to identify early unsuccessful choices. Experimental results are reported, demonstrating that the method is able to improve the efficiency of a topological ATPG in terms of required CPU time and attained fault coverage, especially on medium-sized control-dominated circuits.

Automatic test pattern generation yielding high fault coverage for CMOS circuits has received a wide attention in industry and academic institutions for a long time. Since ATPG is an NP complete problem with complexity exponential to the number of circuit elements, the parallelization of ATPG is an attractive of research. In this paper we describe a parallel sequential ATPG approach which is either run on a standard network of UNIX workstations or, without any changing of the source code, on one of the most powerful high performance parallel computers, the IBM SP2. The test pattern generation is performed in three phases, two for easy-to-detect faults, using fault parallelism with an adaptive limit for the number of backtracks and a third phase for hard-to-detect faults, using search tree parallelism. The main advantage over existing approaches is a dynamic solution for partitioning the fault list and the search tree resulting in a very small overhead for communication without the need of any broadcasts and an optimal load balancing without idle times for the test pattern generators. Experimental results are shown in comparison with existing approaches and are promising with respect to small overhead and utilization of resources.

Performance optimization of automatic test pattern generation (ATPG) algorithms has received considerable attention. While the application of high-performance algorithms is often limited to simple gates such as AND's, OR's, and XOR, the cell libraries of silicon vendors usually contain more sophisticated structures. To deal with this problem, we present a library independent algorithm for the partitioning and analysis of static digital CMOS circuits described at the switch level. The algorithm recognizes inverters, NANDs, and NORs. It also checks whether a partition can set its output to a high impedance state, thus being capable of partitioning large bus structures with tristate gates. Our approach supports existing ATPG algorithms at the gate level. Moreover, it allows a mixed-level approach for ATPG using detailed fault models at the switch level for whatever partitions it is necessary. Our implementation processes in the order of 2000 transistors per second. This is for circuits containing combinational and sequential logic on a state-of-the-art workstation. We processed complete chips with up to 72000 transistors, which is clearly adequate for practical purposes.

The paper describes the design exploration environment of the CASTLE system. The environment allows the exploration of hardware and software for complex processor designs. The exploration is subdivided into the measurement phase and the analysis phase. The measurement phase uses a retargetable compiler to determine the performance for a large number of different processors and different programs. These fine-grained data form the input of the analysis phase. It transforms the data into abstract representations that are visualized for the designer. The results are integrated into an HTML-based framework.

Automatic test pattern generation (ATPG) yielding high fault coverage for CMOS circuits has received a wide attention in industry and academia for a long time. Mixed level test pattern generation offers advantages, since test generation from gate-level netlists has shortcomings regarding fault coverage in complex CMOS gates. A switch-level approach relying on the transistor structure only is too slow and impractical for larger circuits. The first part of this paper describes ATPG with a mixed switch-level and gate-level approach. It combines acceptable performance for large networks with a high fault coverage as well as for nontrivial transistor networks. Patterns generated this way are inherently capable to detect stuck-open faults and transition faults as well as various other fault models on different abstraction levels. In combination with local overcurrent detectors, also stuck-on- and local bridging-faults can be identified. To increase the efficiency of mixed level test generation, a reconvergency analysis is performed and constraints are stored. The second part of this paper deals with mixed level test generation for synchronous sequential circuits. The FOGBUSTER (FOrward propaGation Backward jUstification Sequential Test genERation) algorithm is described and experimental results for the ISCAS '89 benchmark circuits are shown. FOGBUSTER makes use of a forward propagation technique which we show to be more efficient in general than the technique used in BACK.

This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal with very large circuits, but often fail when highly sequential subnetworks are found. On the other hand, symbolic techniques based on Binary Decision Diagrams proved themselves very efficient on small or medium circuits, no matter their sequential complexity. A state-of-the-art structural ATPG is extended by identifying some critical areas in the circuit and resorting to symbolic techniques when such areas need to be considered. Experimental results prove that the combined approach considerably enhances fault coverage while reducing CPU time when compared to a purely topological approach.

Due to the complexity of test generation for stuck-at-faults in synchronous sequential circuits and the permanently increasing problem-size, algorithms solving this problem cannot work with acceptable CPU-time, even on computer systems with very high performance. Relating to this context this paper presents a new testability analysis guiding algorithms for sequential test generation. This testability analysis consists of two separated parts: First, a new technique for the detection of untestable stuck-at-faults; second, heuristics used to guide the decision process in test generation algorithms. Experimental results of sequential benchmark circuits allow us to conclude that our testability analysis provides less CPU-time for sequential test generation than other well-known testability analysis tools.>

Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing.>

A library independent method for the partitioning and analysis of switch-level CMOS circuits is presented. This method is superior to the existing methods for extraction, because it is able to recognize CMOS tristate drivers connected to a bus individually. Moreover, it can improve the state-of-the-art algorithms for the determination of unidirectional signal flow, because its functional analysis is able to recognize groups of transistors which always constitute signal sources. The local functional analysis of the partitions is improved by the exclusion of impossible paths. Additionally, the recognition of fully complementary gates allows the improvement of existing algorithms for signal flow analysis.>

The theoretical background required for a novel approach in the automatic layout generation for CMOS complex gates is described. This approach is directed at the automatic synthesis of complex gate structures using optimized substructures. The focus is on the efficient detection of subgraphs representing existing floorplans of subcells from larger graphs representing complex gates. The data structures and algorithms of the derived program are based on the mathematical description of CMOS switch-level circuits. The foundation of the graph model, called a multiplace graph, is presented in a novel and extended version.>

Automatic test pattern generation yielding high fault coverage also for non-trivial faults in CMOS circuits has found a wide attention in industry and research for a long time. Test generation from gate level netlists is quite efficient, but has shortcomings with respect to fault coverage in complex CMOS gates, while an approach reyling on the transistor structure only is inefficient and virtually impossible for larger circuits. This paper describes mechanisms for coupling switch level and gate elvel test generation towards an efficient mixed level test generator that combines acceptable performance for large networks and high fault coverage also for non-trivial transistor networks. Patterns generated this way are inherently capable to detect interrupt-types of faults and transition faults. In combination with local overcurrent detectors, also stuck-on- and bridging faults can be identified.