Many of the previously-developed multiple-access detection algorithms have assumed knowledge of the time delay, the amplitude, and the phase of each user. This paper presents methods of estimating the amplitudes and phases, both when the time delays are known and when the delays are unknown. In neither case are the transmitted bits assumed to be known. The estimators are unbiased and consistent, and each has a computational complexity linear in the number of users. Simulations are provided to demonstrate performance.>

The problem of simultaneously detecting the information bits and estimating signal amplitudes and phases in a K-user asynchronous direct-sequence spread-spectrum multiple-access communication system is addressed. The joint maximum-likelihood (ML) estimator has a computational complexity that is exponential in the total number of bits transmitted and thus does not represent a practical solution to the problem. An estimator that combines a suboptimum tree-search algorithm with a recursive least-squares estimator of complex signal amplitude is considered. The complexity of this estimator is O(K/sup 2/) computations per decoded bit, and its performance is very close to that of the joint ML receiver. This receiver has the advantage that the transmitted signal powers and phases are extracted from the received signal in an adaptive fashion without using a test sequence.>

Consideration is given to a class of suboptimum detectors for data transmitted asynchronously by K users employing direct-sequence spread-spectrum multiple access (DS/SSMA) on the additive white Gaussian noise (AWGN) channel. The general structure of these detectors consists of a bank of matched filters, a linear transformation that operates on the matched-filter outputs, and a set of threshold devices. The linear transformations are chosen to minimize either a mean-squared-error or a weighted-squared-error performance criterion. Each detector can be implemented using a tapped delay line. The number of computations performed per detected bit is linear in K in each case, and the resulting detectors are thus much simpler than the optimum detector. Under typical operating conditions, these detectors will perform much better than the conventional receiver and often nearly as well as the optimum detector.>

The application of sequential decoding to the detection of data transmitted over the additive white Gaussian noise channel by K asynchronous transmitters using direct-sequence spread-spectrum multiple access (DS/SSMA) is considered. A modification of R.M. Fano's (1963) sequential-decoding metric, allowing the messages from a given user to be safely decoded if its E/sub b//N/sub 0/ exceeds -1.6 dB, is presented. Computer simulation is used to evaluate the performance of a sequential decoder that uses this metric in conjunction with the stack algorithm. In many circumstances, the sequential decoder achieves results comparable to those obtained using the much more complicated optimal receiver.>

A trace-driven simulation study to examine the effect of a two-level cache hierarchy in uniprocessors is reported. A simulation model of a multiple-cycle-per-instruction processor was constructed to estimate the total cycles required to execute a synthetic benchmark. Results show that a second-level cache can be used to increase system performance when main memory access times are large relative to CPU cycle time. For example, the addition of a four-cycle 64 K second-level cache following a one-cycle, 8 K first-level cache increases performance by 15% when used in a system with a 15-cycle primary memory. Second-level caches are shown to be particularly effective when used behind small on-chip caches; adding an 8 K second-level to a 1 K first-level increases performance by 26%, assuming similar parameters. The performance impact of different write strategies and separate instruction and data caches are also evaluated.>