Anticipating silicon response in the presence or process variability is essential to avoid costly silicon re-spins. EDA industry is trying to provide the right set of tools to designers for statistical characterization of SRAM and logic. Yet design teams (also in foundries) are still using classical corner based characterization approaches. On the one hand the EDA industry fails to meet the demands on the appropriate functionality of the tools. On the other hand, design teams are not yet fully aware of the trade-offs involved when designing under extreme process variability. This paper summarizes the challenges for statistical characterization of SRAM and logic. It describes the key features of a set of prototype tools addressing that required functionality together with their application to a number of case studies aiming at enhancing yield at product level.

We present a new method and its implementation that enables design-phase assessment of statistical performance metrics of semiconductor memories under random local and global process variations. Engineers use the tool to reduce design margins and to maximize parametric yield. Results on industry grade 45nm SRAM designs show that this holistic approach is significantly more accurate than the alternatives based on global corners or critical path netlist, which can lead to unexpected yield loss.

This paper presents an automated technique to perform SRAM wide statistical analysis in presence of process variability. The technique is implemented in a prototype tool and is demonstrated on several 45 and 32nm industry-grade SRAM vehicles. Selected case studies show how this approach successfully captures non-trivial statistical interactions between the cells and the periphery, which remain uncovered when only using statistical electrical simulations of the critical path or applying a digital corner approach. The presented tool provides the designer with valuable information on what performance metrics to expect, if manufactured. Since this feedback takes place in the design phase, a significant reduction in development time and cost can be achieved.

Analyzing the stability of an analog circuit is an important part of the circuit design. Several commercial simulators are equipped with special stability analysis techniques. Problems arise when your design kit does not support such simulator. Another issue is when the designer wants to get insight into the sources of the instability to propose a stabilization. This can be done through analyzing the open-loop or the closed-loop transfer function of the circuit. The aim of this paper is to propose an automated analysis method which identifies the nodes to be considered for stabilization. The method does not need to break feedback loops or to manipulate netlists. It only uses AC simulations and does not require the full modified nodal equations. The method is illustrated on 3 design examples: a voltage controlled oscillator (VCO), a reference bias circuit and the common-mode feedback network in a gm-C filter

Substrate noise is a major obstacle for mixed-signal integration. In this paper we propose a fast and accurate high-level methodology to simulate substrate noise generated by large digital circuits. The methodology can handle any substrate type, e.g. bulk-type or EPI-type, and takes into account the effects of interconnect and supply. For each standard cell a substrate macromodel is used in order to efficiently simulate the total system, which consists of a network of such macromodels. For a 40K gates telecom circuit fabricated in a 0.18 mm CMOS process, measurements indicate that substrate noise is simulated by using our methodology within 20% error but several orders of magnitude faster in CPU time than a full SPICE simulation..

The design of analog front-ends of digital telecommunication transceivers requires mixed-signal simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency dependent. This paper describes an analysis and modeling method based on Volterra theory. The method derives bottom-up models of nonlinear analog continuous-time circuits. These behavioral models predict the dominant nonlinear effects using a composition of linear transfer functions and multiplications. This makes it possible to accurately model frequency dependencies and to gain insight into the dominant nonlinear sources of the circuit. The basic models are afterwards described using its multicarrier complex low-pass representation to enable their efficient cosimulation with the digital circuits in a dataflow simulation environment. The multicarrier representation is a direct extension of the classically used complex low-pass equivalent models, which considers the modulation of a single carrier only. The accuracy of the multicarrier representation is higher than classical complex low-pass equivalent models since out-of-band nonlinear distortion is taken into account. The main advantage of the proposed technique is that it yields both insight in the nonlinear behavior at the circuit level and that it provides an important gain in simulation efficiency of RF integrated circuits at the system level. Both aspects are demonstrated on a 5-GHz WLAN design.

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developped for the efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme which switches dynamically towards the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy.

The design of analog front-ends of digital telecommunication transceivers requires simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency dependent. This paper describes a method to derive a bottom-up model of nonlinear analog continuous-time circuits used in communication systems. The models take into account frequency dependence of the nonlinear behavior, making them suitable for wideband applications. Such model consists of a block diagram that corresponds to the most important contributions to the second- and third-order Volterra kernels of the output quantity (voltage or current) of a circuit. The examples in this paper, a high-level model of a CMOS low-noise amplifier and an active lowpass filter, demonstrate that the generated models can be efficiently evaluated in high-level dataflow-type simulations of mixed-signal front-ends and that they yield insight in the nonlinear behavior of the analog front-end blocks.