Due to the immaturity of the manufacturing process, numerous faults often occur in through-silicon vias (TSVs). Prebond TSV testing is crucial in enhancing the performance and yield of chiplet-based integrated chips. However, most existing test methods suffer from the test resolution and hard-to-detect weak faults. A novel prebond TSV test method based on the pulse is proposed to improve the test circuit. By introducing pMOS as a driver in pulse detection, TSV leakage faults can be directly tested, thus improving the resolution of leakage faults’ detection. In addition, the range of test pulsewidth to digital code conversion is effectively improved by the ring oscillator (RO) for coarse detection and pulse shrinking for fine detection, avoiding the problem of large overheads that would be brought about by solely increasing the pulse shrinking chain. The results validated by HSPICE simulation show that it can detect open faults, resistive open faults with$R_{\text {open}} \gt $$0.9~{\mathrm {K}} {\mathrm {\Omega }}$, leakage faults with$R_{\text {leak}} \lt $$30~{\mathrm {G}} {\mathrm {\Omega }}$, and compound faults consisting of resistive open faults and leakage faults.

Unpredictable true random numbers are required in security technology fields such as information encryption, key generation, mask generation for anti-side-channel analysis, algorithm initialization, and so on. At present, the true random number generator (TRNG) is not enough to provide fast random bits by low-speed bits generation. Therefore, it is necessary to design a faster TRNG. This work presents an ultra-compact TRNG with high throughput based on a novel extendable dual-ring oscillator (DRO). Owing to multiple bits output per cycle in DRO can be used to obtain the original random sequence, the proposed DRO achieves a maximum resource utilization to build a more efficient TRNG, compared with the conventional TRNG system based on ring oscillator (RO), which only has a single output and needs to build multiple groups of ring oscillators. TRNG based on the 2-bit DRO and its 8-bit derivative structure has been verified on Xilinx Artix-7 and Kintex-7 FPGA under the automatic layout and routing and has achieved a throughput of 550 Mbps and 1,100 Mbps, respectively. Moreover, in terms of throughput performance over operating frequency, hardware consumption, and entropy, the proposed scheme has obvious advantages. Finally, the generated sequences show good randomness in the test of NIST SP800-22 and Dieharder test suite and pass the entropy estimation test kit NIST SP800-90B and AIS-31.

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.

This study presents a pure digital scalable mixed entropy separation structure for the physical unclonable function (PUF) and true random number generator (TRNG), which is implemented on Xilinx field-programmable gate arrays (FPGAs). The mixed entropy separation structure in this study is to solve the problems of unstable output in the existing PUF structure and the poor scalability of the TRNG and PUF design. The proposed design has the following innovations: 1) concept of sensitive entropy and the corresponding processing method are proposed for the first time; 2) design does not need to modify the internal design of the entropy source, and it is suitable for most entropy source arrays; and 3) adjustable PUF bit width and TRNG throughput enhance the scalability of the architecture under different requirements. The structure is simulated and validated on two Xilinx FPGAs and tested under nominal working conditions. The results show that the 512-bit PUF entropy source after treatment is 92.7% more stable than the 1024-bit entropy source before treatment, the random number after treatment passes all types of randomness tests, and the minimum entropy is more than 0.8. Under various conditions within the ranges of 0 °C–80 °C and 0.8–1.2 V, the TRNG output remains stable after treatment; the maximum intra-Hamming distance of the treated PUF is 5.1028%, and the average intra-Hamming distance is 2.7065%.

Adaptive testing is a promising approach that practically ensures cost reduction and reliability for test strategy. In adaptive testing, the test content or pass/fail limits are not fixed as in conventional test, but depend on other test results of the currently or historically tested data. Based on recent progress in machine learning, a new Long Short-Term Memory (LSTM) which is more advanced than simple Recurrent Neuron Network (RNN) is proposed for defect screening. The simulation results have been compared with the other deep learning and traditional methods when patterns are increased and decreased. The comparisons show that the proposed RNN-based LSTM method has achieved remarkable improvements, i.e. 4.3% accuracy improvement and 2.32s time reduction during the test process.

Since the physical defects such as resistive open and leakage in through silicon vias (TSVs) caused by immature manufacturing techniques tend to undermine the reliability and yield of 3-D integrated circuits, it is very important to test the TSV as early as possible in the fabrication process. There are some shortcomings in the existing prebond TSV test techniques, such as incomprehensive fault coverage, large area overhead, and additional test time. To overcome these problems, a noninvasive solution for prebond TSV test based on pulse shrinking is proposed in this paper. This method makes use of the fact that defects in TSV lead to variation in the propagation delay-the rise and fall times are first transformed into pulse width, and the pulse shrinking technique is used to digitize the pulse width into a digital code which is then compared with an expected value for a fault-free TSV. Experiments on defect detection are carried out using HSPICE simulations with realistic models for 45-nm CMOS technology. The results show that the proposed method performs better than the existing methods in terms of fault coverage, area overhead, and test time.

True random number generator (TRNG), essential component in cryptographic equipment, which can generate unpredictable and irreproducible key string has an important effect on information encryption. In this work, a novel low-cost, high-efficiency true random number generator based on the ring oscillator is implemented on FPGAs. Forming a tapped delay line by utilizing the fast carry logic on FPGA, we have improved the efficiency of the entropy extraction from the jitter of single transition event rather than multiple jitter accumulation like most RO-based TRNGs. In order to achieve low cost and high throughput, the delay of the ring oscillator has been optimized by deeply studying LUT structure and routing resources. The proposed architecture has been validated on Xilinx Virtex-6 FPGA, which obtains a high throughput of about 100 Mbps while occupying just 25 slices and provides robustness across a wide range of temperature (0 °C ~ 80 °C), voltage (0.9 V ~ 1.1 V) and process variation (multiple chips). And the generated random bitstreams have passed all tests in the NIST statistical test suite.

This paper describes a novel all-digital true rand-om number generator (TRNG) in SRAM-based field programable gate arrays (FPGAs), which utilizes vernier technique to high precisely quantize random edge jitter caused by thermal noise in order for on-die entropy extraction. The TRNG is implemented in three ML605 platforms and experimental result shows that the TRNG presents a high quality of randomness (passing all NIST random tests with high p-values), a high throughput of 127 Mbps, and a good tolerance to bias phenolmenon induced by process, voltage, and temperature (PVT) variations.

This paper presents an aging-temperature-and-propagation induced pulse-broadening aware soft error rate (SER) estimation for nano-scale CMOS. To calculate the SER of circuits, logical masking effect, electrical effect and timing masking effect should be considered. In logical masking effect, a hybrid method using four-value probability and two-value probability is used; in electrical effect, pulse broadening induced by aging, temperature and PIPB is measured; in timing masking effect, failure rate of circuits is calculated. Finally, the SER of circuits is calculated using our proposed framework. Simulation results show that the average SER-increase of ISCAS'85 circuits is 61.2% under temperature from 0 to 120°C, 17.5% under aging from 0 to 10 years, and 137.8% under temperature-and-aging from 0°C-0 year to 120°C-10 years. The SER estimation efficiency and accuracy are ensured using Monte Carlo method.

Physical Unclonable Functions (PUFs) promise cheap, efficient, and secure identification and authentication of devices, especially in FPGAs, which have been widely used. Various PUF implementation techniques have been proposed to translate chip-specific variations into a unique chip ID. It is difficult to guarantee the stability of the chip ID generation due to the complex operating environment. To solve this problem, in this paper, the Programmable Delay Lines (PDLs) was utilized to configure the ring oscillator to improve the stability of ID gener-ation. Compared with the original RO PUF, the proposed structure does not add extra overhead, but instead saves resources due to the compact layout. Experimental results demonstrate that the chip ID generated by our configurable ring oscillator (RO) PUFs is random (passing the NIST randomness test), and multiple measurements under a wide range of operating environments show that the proposed PUF is highly reliable (the bit flip rate is reduced from approximately 1.0% to 0 at nominal temperature and voltage conditions).

This paper presents a novel double-node upset (DNU) tolerant latch through radiation-hardening-by-design combined with layout technique. The latch mainly comprises 6 interlocked cross-coupled input-split inverters. Due to the special feedback rules for the internal nodes, many interlocked feedback loops are constructed in the latch and the following robustness is achieved: 1) In the case of 0 being held, the latch can self-recover from any single node upset (SNU), any DNU including double-adjacent-node upset (DANU) and double-separated-node upset (DSNU); 2) In the case of 1 being held, the latch can self-recover from any SNU, any DANU and partial DSNU. However, using layout technique, as for any DSNU-sensitive node-pair, the nodes are separated, thus the latch can avoid any DSNU. Simulation results demonstrate the robustness of the proposed latch. Besides, compared with typical existing DNU hardened latch designs, the proposed latch approximately saves 80.25% area-power-delay product on average.

This paper presents a high-performance, low-cost, and double node upset (DNU) tolerant latch design. The latch mainly constructs from a 3-input Muller C-element at the output stage and a single node upset resilient cell for keeping data, and the cell mainly consists of triple mutual feedback 2-input Muller C-elements, thus the latch is DNU tolerant. Using fewer CMOS transistors, clock gating technique, and high-speed transmission path, the latch also performs with lower cost penalties. Simulation results have demonstrated the DNU tolerability and a ~97.78% area-power-delay product saving for the latch design on average compared with the DNU tolerant latch designs.

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.

Ever-growing test data volume and test power dissipation poses significant cost and security challenges in testing core-based system-on-chip (SoC). In this paper, a test pattern recombination technique is proposed to improve test data compression and decrease scan test power dissipation. The proposed technique first analyzes the entropy of a test set, which is used to determine the maximum compression ratio, and then divides the test set into a group of patterns that are used as scan slices for scan test based on multi-scan chains. The probability of the compatibility between the patterns in every vector is calculated, according to which the patterns of each test vector are recombined so that the patterns with high compatible probability are placed closely. Finally, for all the test vectors in a test set, a unified arrangement order for their patterns is determined based on the goal that the test set can be compressed and the scan test power dissipation can be decreased to advantage. The proposed scheme is applied to ISCAS89 test benchmarks and their MinTest test sets are used. The experimental results show that compared to the recently presented scheme, the proposed technique can effectively ensure a high data compression ratio and reduce shift power dissipation during testing.

A precomputed core test set contains a large number of don't cares (x's) that can be effectively exploited to improve test data compression (TDC). Extending pattern run-length coding, we present a novel strategy that propagates thex's of a reference pattern to a new reference pattern in such a way that the reference pattern is xor-ed with the pattern to be encoded. Thex-propagating strategy can increase the probability of a reference pattern being coding-compatible with the pattern to be encoded, and its validity can be established by filling somex's of the already encoded patterns in backtracing way. How our strategy is used for TDC is demonstrated. Experimental results for large ISCAS89 benchmarks show that, compared to the recently proposed schemes, our technique can effectively improve compression and simplify on-chip decoder, and work better when used for core-unified TDC.

In this paper, a BIST scheme based on selecting state generation of folding counters is presented. LFSR is used to encode the seeds of the folding counters, where folding distances (or indexes) are stored to control deterministic test patterns generation, so that the generated test set is completely equal to the original test set. This scheme solves compression of the deterministic test set and overcomes overlapping and redundancy of test patterns produced by the different seeds. Experimental results prove that it not only achieves higher test data compression ratio, but also efficiently reduces test application time, and that the average test application time is only four percent of that of the same type scheme.