Power-gating (PG) architectures employing nonvolatile state/data retention, called nonvolatile PG (NVPG), are expected as a highly efficient energy reduction technique for high-performance microprocessors and mobile/wearable SoC devices. In this paper, NVPG architecture for SRAM is demonstrated. A 1kb nonvolatile SRAM (NV-SRAM) array with the peripheral circuits is implemented using 65nm silicon-on-thin-buried-oxide (SOTB) technology. The cell design and array architectures for the NV-SRAM are discussed from the viewpoints of the stability and energy efficiency. Energy performance of the NVPG architecture for NV-SRAM with various array sizes is also systematically analyzed using a performance index of break-even time (BET). The array structure and its peripherals strongly affect BET. The body-bias-induced leakage reduction for the peripherals is highly effective at reducing BET. The NVPG architecture with NV-SRAM would be adaptable to core-level power-gating of multi-/many-core processors and SoC devices, and it could also be promising as a solution for the dark silicon problem.

Spin transistors are a new concept device that unites an ordinary transistor with the useful functions of a spin (magnetoresistive) device. They are expected to be a building block for novel integrated circuits employing spin degrees of freedom. The interesting features of spin transistors are nonvolatile information storage and reconfigurable output characteristics: these are very useful and suitable functionalities for various new integrated circuit architectures that are inaccessible to ordinary transistor circuits. This article reviews the current status and outlook of spin transistors from the viewpoint of integrated circuit applications. The device structure, operating principle, performance, and features of various spin transistors are discussed. The fundamental and key phenomena/technologies for spin injection, transport, and manipulation in semiconductors and the integrated circuit applications of spin transistors to nonvolatile logic and reconfigurable logic are also described.

This article reviews a recently proposed new class of spin transistors referred to as spin metal-oxide-semiconductor field-effect transistors (spin MOSFETs), and their integrated circuit applications. The fundamental device structures, operating principle, and theoretically predicted device performance are presented. Spin MOSFETs potentially exhibit significant magnetotransport effects, such as large magneto-current, and also satisfy important requirements for integrated circuit applications such as high transconductance, low power-delay product, and low off-current. Since spin MOSFETs can perform signal processing and logic operations and can store digital data using both charge transport and spin degrees of freedom, they are expected to be building blocks for memory cells and logic gates in spin-electronic integrated circuits. Novel spin-electronic integrated circuit architectures for nonvolatile memory and reconfigurable logic employing spin MOSFETs are also presented.