In this paper, a low-power design of Viterbi decoder is presented. Based on the adaptive Viterbi algorithm, we use a dynamic setting method to set various threshold values for different decoding stages under a particular SNR and efficient reduce the average number of survivor paths. Furthermore, a flexible soft intellectual property core and an auxiliary software system for low-power Viterbi decoder are proposed. In the VLSI realization, we apply the clock-gating technique to disable the activation of registers for nonsurvivor paths. Hence, the power consumption can be reduced. Compared with others, our design requires the lower power consumption for the same SNR condition.

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.

In this paper, a distributed diagnostic fault simulation for sequential circuits by dynamic fault partitioning is proposed, in which the indistinguishable faults for all the detectable faults are obtained from different machines. Several ISCAS89 benchmark circuits have been experimented on. For a circuit s35932, less than one hour of CPU time is spent by using 4 SUN SPARC stations II.

In this paper, we present an efficient diagnostic simulation method for combinational circuits. Two concepts are incorporated in this method. We adopt the critical line concept so that only stems, instead of all the faults, need to record the primary output responses and introduce the parallel simulation concept to propagate the effects of all the stems simultaneously. With these two approaches, our diagnostic simulator is efficient in speed and memory usage compared to an existed one.>