Scan designs alleviate the test generation problem for sequential circuits. However, scan operations substantially increase the total number of test clocks during test application stage. Classical methods used to solve this problem perform test compaction and obtain fewer test vectors. In this paper we show that such a strategy does not always reduce the test clocks or test application time. Our approach is to associate a scan strategy function with each test vector during test generation for circuits with full or partial scan. The paper presents two algorithms to generate test sequences that reduce the number of test clocks required to apply the test sequences. The algorithms are based on: (1) heuristics that determine the need for scan operations; and (2) controlling sequential test generation process by choosing an appropriate target fault. In this paper we define and investigate different scan strategies for full and partial scan designs. We propose approximate measures that can be used for selection of a target fault during sequential test generation. These concepts are integrated into the algorithms Test Application time Reduction for Full scan (TARF) and Test Application time Reduction for Partial scan (TARP). The algorithms are implemented, and their efficiencies are demonstrated by using them for a set of ISCAS sequential benchmark circuits. The experiments show that, in full scan designs, TARF generated vectors require 36% fewer test clocks compared to the vectors from COMPACTEST that produces near optimal test sets. Similarly for partial scan designs, TARP achieves over 30% cumulative test clock reduction compared to the results from FASTEST which produced generally fewer vectors than other ATPG systems.>

Partial scan design technique is often preferred to full scan because the use of smaller number of scan flip-flops leads to less performance degradation and less overhead. However, the number of clocks required to apply a test vector is proportional to the number of flip-flops in the scan path whenever scan is performed. This tends to increase the test application considerably. In this paper we presents an algorithm to generate a test with fewer test clocks for partial scan designs by using sequential test generation and scan strategies. The objective is to find a test that requires less test clocks while achieving high fault coverage. The algorithm, Test Application time Reduction for Partial scan design (TARP), is implemented and tested on a set of ISCAS sequential benchmark circuits. The algorithm produces a test with substantial reduction in the number of test clocks, compared to a test in which each test vector is associated with a scan operation.>

This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of Initial Timeframe Algorithm and correct implementation of a solution to the Previous State Information Problem. The Initial Timeframe Algorithm, one of the most important aspects of the test generator, determines the number of timeframes required to excite the fault for which a test is to be derived and the number of timeframes required to observe the excited fault. Correct determination of the number of timeframes in which the fault should be excited (activated) and observed saves the test generator from performing unnecessary search in the input space. Test generation is unidirectional, i.e., it is done strictly in forward time, and flip-flops in the initial timeframe are never assigned a state that needs to be justified later. The algorithm saves both the good and the faulty machine states after finding a test to aid in subsequent test generation. The Previous State Information Problem, which has often been ignored by existing test generators, is presented and discussed in the paper. Experimental results are presented to demonstrate the effectiveness of the algorithm.>

An algorithm for generating a test with fewer test clocks for full scan designs by using combinational and sequential test generation algorithms adaptively is presented. Heuristics combining tests measures and scan strategies are introduced. The algorithm, 'Test Application time Reduction for Full scan designs' (TARF), is implemented and tested on a set of ISCAS sequential benchmark circuits. The results show that TARF achieves the same test coverage as combinational test generators but with fewer test clocks.>