A framework is presented to identify an optimal accelerated test region and accelerated test conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown (TDDB). Both gate-oxide breakdown and middle-of-line (MOL) TDDB are investigated. Separate test regions are identified for each wearout mechanism. Two digital circuits, an 8-bit fast Fourier transform (FFT) circuit and a Leon3 microprocessor are used to demonstrate the capability of the framework. The lifetimes of standard cells are combined to compute the circuit lifetime, by combining the Weibull distributions that characterize the lifetime distribution of each of the standard cells. The errors in estimating wearout parameters consist of two parts: the error in estimating the wearout parameters at accelerated test conditions and the forecasting accuracy at use conditions. By estimating the errors in wearout parameters at accelerated test conditions, the optimal accelerated test region is found by determining the test conditions producing a minimal error. Test conditions are selected by minimizing the error at use conditions. Given a forecasting error target, the required sample size at each test condition is found. This work also considers the impact of variation in circuit size, type, and process parameters on the selection of optimal test conditions.

Biological neurons seem able to compute with noise reliably, or even to use noise to achieve probabilistic inference. This paper introduces two neuro-inspired algorithms and their implementation in the Very Large Scale Integration (VLSI). By generalising data variability with noise, the algorithms are able to classify noisy data more reliably. The VLSI implementation further demonstrates the feasibility of utilising electronic noise for stochastic computation. To exploit the intrinsic noise of transistors for computation, two transistors with enhanced and adaptable noise are further developed and modelled. These technologies would allow us to compute with noisy devices just like how the brain computes with noisy neurons.

This paper presents a phase-locked loop design with the supply-regulated voltage-controlled oscillator to enhance power supply immunity. The supply regulator associated with the voltage-controlled oscillator (VCO) employs the bandwidth adaption scheme by adjusting the bias current of OP-Amp. Measurement results show that the tuning range is from 0.24 to 2.4 GHz, and the output long term RMS jitter is 1.3% of the VCO period. The output clock has a sensitivity of 0.3% clock period with 1% supply disturbance when operating at 2.4 GHz. The PLL is realized with the standard 0.18-μm CMOS technology. The active area occupies 0.18 mm2, and the maximum power dissipation is 18 mW.

The Diffusion Network(DN) is a stochastic recurrent network which has been shown capable of modeling the distributions of continuous-valued, continuous-time paths. However, the dynamics of the DN are governed by stochastic differential equations, making the DN unfavourable for simulation in a digital computer. This paper presents the implementation of the DN in analogue Very Large Scale Integration, enabling the DN to be simulated in real time. Moreover, the log-domain representation is applied to the DN, allowing the supply voltage and thus the power consumption to be reduced without limiting the dynamic ranges for diffusion processes. A VLSI chip containing a DN with two stochastic units has been designed and fabricated. The design of component circuits will be described, so will the simulation of the full system be presented. The simulation results demonstrate that the DN in VLSI is able to regenerate various types of continuous paths in real-time.

A frequency synthesizer combining offset phase-locked loop (OPLL) and direct-digital synthesis (DDS) is presented in this paper. DDS is for channel selection as it inherits fast settling and fine resolution characteristics. OPLL structure helps to lower the DDS operation speed thus reduce the power dissipation. Compared with the conventional PLL, this structure relieves the tradeoff between loop bandwidth and settling time requirement. System analysis shows that this structure can meet the stringent requirement of DCS1800. This structure is designed with a 0.18 mum CMOS process. Excluding of DDS, the synthesizer core dissipates 9.5mW from a 1.8V supply