In analog neuromorphic chips, designers can embed computing primitives in the intrinsic physical properties of devices and circuits, heavily reducing device count and energy consumption, and enabling high parallelism, because all devices are computing simultaneously. Neural network parameters can be stored in local analog non-volatile memories (NVMs), saving the energy required to move data between memory and logic. However, the main drawback of analog sub-threshold electronic circuits is their dramatic temperature sensitivity. In this paper, we demonstrate that a temperature compensation mechanism can be devised to solve this problem. We have designed and fabricated a chip implementing a two-layer analog neural network trained to classify low-resolution images of handwritten digits with a low-cost single-poly complementary metal-oxide-semiconductor (CMOS) process, using unconventional analog NVMs for weight storage. We demonstrate a temperature-resilient analog neuromorphic chip for image recognition operating between 10°C and 60°C without loss of classification accuracy, within 2% of the corresponding software-based neural network in the whole temperature range.

Some applications require electronic systems to operate at extremely high temperature. Extending the operating temperature range of automotive-grade CMOS processes — through the use of dedicated design techniques — can provide an important cost-effective advantage. We present a second-order discrete-time delta-sigma analog-to-digital converter operating at a temperature of up to$250~^{\circ }$C, well beyond the$175~^{\circ }$C qualification temperature of the automotive-grade CMOS process used for its fabrication (XFAB XT018). The analog-to-digital converter incorporates design techniques that are effective in mitigating the adverse effects of the high temperature, such as increased leakage currents and electromigration. We use configurations of dummy transistors for leakage compensation, clock-boosting methods to limit pass-gate cross-talk, and we optimized the circuit architecture to ensure stability and accuracy at high temperature. Comprehensive measurements demonstrate that the analog-to-digital converter achieves a signal-to-noise ratio exceeding 93 dB at$250~^{\circ }$C over a signal bandwidth of 146 Hz, with an effective number of bits of 12, and a power consumption of only 44 mW. The die area of the converter is only 0.065 mm2and the area overhead of the high-temperature mitigation circuits is only 13.7%. The Schreier Figure of Merit is 140 dB at the maximum temperature of$250~^{\circ }$C, proving the potential of the circuit for reliable operation in challenging applications such as gas and oil extraction and aeronautics.

Interoperability is one of the main issues concerning the Internet of Things (IoT). The Arrowhead Framework (AHF) is an open-source platform that aims at tackling this problem. In this work, we first integrate a set of legacy IoT devices (i.e., an ECG and a smart plug) into the AHF by leveraging W3C Web of Things (WoT) as an interface between the two worlds. The result is an architecture where AHF consumers are deployed in a local cloud and consume Web Things, which can be deployed on IoT devices as well as on servers at the network edge to provide edge computing services. In this context, IoT device mobility raises a problem. When the IoT device moves, indeed, the edge-hosted service needs to follow it to preserve proximity, which is key to edge computing. In this case, the IP addresses of both the Web Things (i.e., the one hosted on the IoT device and the one hosted at the edge) may change, causing problems of mutual reachability after mobility/migration. WoT does not currently handle this issue. In this work, we extend WoT in this direction and evaluate our approach over a small-scale edge computing testbed.

We propose a subthreshold CMOS voltage reference operating with a minimum supply voltage of only 150 mV, which is three times lower than the minimum value presently reported in the literature. The generated reference voltage is only 17.69 mV. This result has been achieved by introducing a temperature compensation technique that does not require the drain-source voltage of each MOSFET to be larger than 4kT/q. The implemented solution consists in two transistors voltage reference with two MOSFETs of the same threshold-type and exploits the dependence of the threshold voltage on transistor size. Measurements performed over a large sample population of 60 chips from two separate batches show a standard deviation of only 0.29 mV. The mean variation of the reference voltage for VDDranging from 0.15 to 1.8 V is 359.5 μV/V, whereas the mean variation of VREFin the temperature range from 0 °C to 120 °C is 26.74 μV/°C. The mean power consumption at 25 °C for VDD= 0.15 V is 26.1 pW. The occupied area is 1200 μm2.

This paper presents the first parameterized, SPICE-compatible compact model of a Graphene Nano-Ribbon Field-Effect Transistor (GNRFET) with doped reservoirs that also supports process variation. The current and charge models closely match numerical TCAD simulations. In addition, process variation in transistor dimension, edge roughness, and doping level in the reservoir are accurately modeled. Our model provides a means to analyze delay and power of graphene-based circuits under process variation, and offers design and fabrication insights for graphene circuits in the future. We show that edge roughness severely degrades the advantages of GNRFET circuits; however, GNRFET is still a good candidate for low-power applications.

The quest for developing graphene-based nanoelectronics puts new requirements on the science and technology of device modeling. It also heightens the role of device modeling in the exploration and in the early assessment of technology options. Graphene-based nanoelectronics is the first form of molecular electronics to reach real prominence, and therefore the role of single atoms and of chemical properties acquires more relevance than in the case of bulk semiconductors. In addition, the promising perspectives offered by band engineering of graphene through chemical modifications increase the role of quantum chemistry methods in the assessment of material properties. In this paper, we review the multiphysics multiscale (MS) approaches required to model graphene-based materials and devices, presenting a comprehensive overview of the main physical models providing a quantitative understanding of the operation of nanoscale transistors. We especially focus on the ongoing efforts to consistently connect simulations at different levels of physical abstraction in order to evaluate materials, device, and circuit properties. We discuss various attempts to induce a gap in graphene-based materials and their impact on the operation of different transistor structures. Finally, we compare candidate devices in terms of integrated circuit performance and robustness to process variability.

This paper describes a physics-based semi-analytical model for Schottky-barrier carbon nanotube (CNT) and graphene nanoribbon (GNR) transistors. The model includes the treatment of (i) both tunneling and thermionic currents, (ii) ambipolar conduction, i.e., both electron and hole current components, (iii) ballistic transport, and (iv) multi-band propagation. Further, it reduces the computational complexity in the two critical and time-consuming steps, namely the calculation of the tunneling probability and the self-consistent evaluation of the the surface potential in the channel. When validated against NanoTCAD ViDES, a quantum transport simulation framework based on the non-equilibrium Green's function method, it is several orders of magnitude faster without significant loss in accuracy. Since the model is physics-based, it is parameterizable and can be used to study the effect of common parametric variations in CNT diameter and GNR width, Schottky-barrier height, and insulator thickness.

We present the design of a circuit, implemented in a standard 0.35 μm CMOS process, that provides a bias current practically independent of temperature and process variations. Experimental results show that the proposed circuit provides a reference current with a temperature coefficient of 44ppm/°C over a range from 0 to 80 °C. The reference current is generated by exploiting a MOS transistor as current defining element, instead of a resistor, allowing us to achieve a relative standard deviation due to process variations of 2% . The minimum supply voltage is 1.3 V and the minimum supply current is 36 nA. The line sensitivity is 569ppm/V. The chip area is 0.035mm2.

The design of an on-chip RC-based oscillator, implemented in a standard 0.35 μm CMOS process, without any external component, is presented. The proposed oscillator provides a clock signal at a frequency of about 80 KHz with a temperature coefficient smaller than 842 ppm/°C over a temperature range from 0 to 80°C and a standard deviation due to process variations smaller than 4%, without any external trimming. The proposed oscillator operates with a supply voltage of 1 V and has a power consumption of about 1 μW at room temperature. The chip area is 0.24 mm2.

We present the design of a flash memory for passive RFID transponders, implemented in a standard - single poly - 0.35 mum CMOS process. The memory has 128 bits, sufficient for example to contain the EPC code for Class 0 tags, and is able to perform a complete read operation of all 128 bits with an access time of about 10 ms and a power consumption of only 160 nW. In the erase/program mode Fowler-Nordheim tunneling is used, and all 128 bits can be written in 0.8 s with a power consumption of about 3 muW. Such power causes an acceptable reduction of the operating range during a write operation to 1.74 m in the 2.45 GHz ISM band and 4.66 m in the UHF ISM band, for a transmitter EIRP of 500 mW, with respect to the read operating range, where 4 m at 2.45 GHz and 10.5 m at 916 MHz are achieved