This work presents a multibit$\Delta \Sigma $time-to-digital converter (TDC) employing a space–time averaging (STA) technique, designed for ultrawideband (UWB) transceivers to achieve fine-resolution time-of-flight (ToF) ranging. The proposed TDC offers both high time resolution and strong immunity to bit errors. By dynamically controlling the input reference signals of multiple phase detectors (PDs), the STA technique significantly reduces the quantization error of the$\Delta \Sigma $TDC, thereby achieving fine time resolution with a limited oversampling ratio (OSR). Additionally, by introducing a delay in the PD reset path, the TDC provides strong immunity to bit errors caused by UWB receiver misdetection. Implemented in 65-nm CMOS, the proposed multibit$\Delta \Sigma $TDC achieves a root-mean-square (rms) error of 14.43ps with an OSR of 50, consuming$276.5~\mu $W at a 10-MHz clock frequency from a 1-V supply.

This paper presents a low-noise class-F23voltage-controlled oscillator (VCO) with harmonic resonance expansion and$2^{\mathrm {nd}}$/$3^{\mathrm {rd}}$-harmonic outputs for multiband mm-wave applications. By using a single four-coil transformer to extend the common-mode (CM) and differential-mode (DM) harmonic resonance bandwidths, the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic resonances can be acquired without additional frequency alignment calibration. Meanwhile, benefiting from the favorable differential response at the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic frequencies, the corresponding harmonic frequency outputs are extracted, simultaneously. Fabricated in 65-nm CMOS process, the proposed VCO achieves a frequency tuning range (FTR) of 20.8% from 10.71 GHz to 13.20GHz with 1-MHz offset phase noise (PN) from -117.4 to -114.5 dBc/Hz, while consuming 7.8-9.8 mW at 0.6 V. The VCO core area is only 0.054 mm2and the flicker noise corner is 310-450 kHz. The figure-of-merit (FoM) at 10-MHz offset scores 189.8-191.7 dBc/Hz. The harmonic outputs achieve a FTR of 21.42-26.40 GHz and 32.13-39.60 GHz, with a 1-MHz-offset PN from –110.5 to –107.5 dBc/Hz and –107.6 to –104.8 dBc/Hz.

Traditional wake-up receiver (WuRX) systems based on voltage-domain comparators for weak signal detection can readily suffer from false triggering due to noise. To address this issue, this work analyzes the mechanism of noise-induced failure in traditional voltage-domain comparator and proposes a time-domain comparator (TDCMP) scheme based on time-domain integration. By temporally integrating the input signal, the noise immunity of the comparator is significantly enhanced. To suppress process, supply voltage, and temperature (PVT) drift in the TDCMP, this work designs a frequency-locked loop (FLL) that employs a voltage-controlled oscillator (VCO) isomorphic to the TDCMP’s voltage-controlled delay line (VCDL) for drift calibration while simultaneously providing the clock signal for the WuRX. Implemented in a 65-nm CMOS process, the core chip area is 0.23 mm2, with a total system power consumption of 20.9 nW. The measurement results demonstrate that the proposed TDCMP enhances the WuRX sensitivity by 4 dB.

This paper describes a balanced frequency shift keying (FSK) modulation, namely quasi-balanced FSK (QB-FSK), for energy-efficient high-data-rate communication. Not suffering from data-pattern dependency, the proposed modulation method enables frequency modulation (FM) over 100 Mb/s by utilizing a wideband phase-locked loop (PLL). The QB-FSK signal is generated with the same baseband clock frequency as the non-return zero (NRZ)-coded binary FSK (BFSK) signal, resulting in improved bandwidth efficiency compared to other balanced FSK signals. For demodulation, the receiver employs a sideband energy detection (SB-ED) method. A FM discriminator converts the QB-FSK signal to an on-off keying (OOK) signal. After that, a band-pass filter (BPF) is used to filter out 1/f noise and dc offset. Based on the proposed QB-FSK modulation and the SB-ED method, a prototype FSK transceiver is implemented in 65-nm CMOS for high-data-rate sub-6-GHz proprietary wireless connectivity. The receiver successfully demodulates data at a rate of 200 Mb/s with a sensitivity of –67 dBm, while the transmitter can achieve a maximum data rate of 400 Mb/s. The 200-Mb/s transceiver achieves an energy efficiency of 0.14 nJ/b.

This paper describes an IR-UWB transmitter with an asymmetric pulse which is featured with a steep rising edge and a slow falling edge. The proposed asymmetric pulse not only achieves a better ranging resolution but also reduces the intersymbol interference (ISI) for high data rate communication. For low data rate communication, a frequency hopping (FH) method is applied to the transmitter to enhance the link margin. The proposed UWB transmitter is designed in 65nm CMOS. Compared to the conventional triangle pulse, the ranging variation of the proposed asymmetric pulse is reduced from 120ps to 10ps over process, voltage and temperature (PVT) variations, the transmitter achieves the maximum data rate of 500Mb/s with a pulse energy of 11.5pJ/bit while meeting the UWB spectral mask.