Similarity search has drawn significant attention due to the growing demand for AI prompt engineering, which leverages retrieval-augmented generation (RAG) systems to maximize the efficiency of large language models (LLMs). Improving the performance of memory-intensive data retrieval processes using approximate nearest neighbor search (ANNS) algorithms has become increasingly crucial for delivering high-quality generative AI services.In this work, we propose Q-VESA, a software-hardware collaborative solution designed to accelerate low-precision graph-based vector search while preserving recall rates comparable to high-precision. We perform a comprehensive analysis of hierarchical navigable small-world (HNSW), one of the most promising graph-based ANNS methods, using recent datasets tailored for RAG systems. Unlike standard vector database datasets, vector data used in LLMs present unique challenges for low-precision search. To address these, we introduce software-oriented precision partitioning techniques that enable mixed-precision computations during graph traversal without compromising hardware performance. The Q-VESA architecture is developed with two key innovations: a database restructuring scheme with vector data segments, and a dedicated accelerator design to maximize throughput in distance computations. Experimental results demonstrate that Q-VESA on a CPU system achieves query-per-second (QPS) speedups of up to 1.81× in the SIMD execution mode. Furthermore, leveraging minimal area overhead, the ASIC implementation delivers an additional speedup of up to 58.3×, 16.5× and 1.5× compared to the CPU, GPU and the state-of-the-art ASIC-based accelerator, respectively.

As the system complexity increases, the simulation performance becomes one of the most important issues in virtual prototyping. Parallel simulation is a fascinating technique for high-speed simulation utilizing state of the art multi-core processors on a host workstation, but the efficiency of the parallel simulation is low because of the synchronization and communication overhead and unbalanced workloads among cores in the host. This paper proposes a novel technique, hierarchical multi-threading for the efficient parallel simulation of SystemC models where the host cores are able to be maximally utilized with the same number of thread groups. We also present an efficient synchronization and dynamic load balancing scheme for the proposed parallel simulation. Experimental results show that the proposed method achieves speed-up of from 2.9 to 3.3 in quad-core host workstation.

The latest biomedical applications require low energy consumption, high performance, and wide energy-performance scalability to adapt to various working environments. In this study, we present ULP-SRP, an energy-efficient reconfigurable processor for biomedical applications. ULP-SRP uses a Coarse-Grained Reconfigurable Array (CGRA) for high-performance data processing with low energy consumption. We adopted a compact-size CGRA and modified it to support dynamically switchable three performance modes with fine-grained power gating in order to further optimize the energy consumption. The energy-performance scalability is also accomplished with multiple performance modes and a Unified Memory Architecture (UMA). Experimental results show that ULP-SRP achieved 59% energy reduction compared to previous works. A technique of dynamic CGRA mode changing gives 18.9% energy reduction. ULP-SRP is a good candidate for future mobile healthcare devices.

Coarse Grained Reconfigurable Architecture (CGRA) achieves high performance by exploiting instruction-level parallelism with software pipeline. Large instruction memory is, however, a critical problem of CGRA, which requires large silicon area and power consumption. Code compression is a promising technique to reduce the memory area, bandwidth requirements, and power consumption. We present an adaptive code compression scheme for CGRA instructions based on dictionary-based compression, where compression mode and dictionary contents are adaptively selected for each execution kernel and compression group. In addition, it is able to design hardware decompressor efficiently with two-cycle latency and negligible silicon overhead. The proposed method achieved an average compression ratio 0.52 in a CGRA of 16-functional unit array with the experiments of well-optimized applications.

There has been extensive research on mapping and scheduling tasks on a many-core SoC. However, none considers the optimization of communication types, which can significantly affect performance, energy consumption, and local memory usage of the SoC. This paper presents an approach to automatic mapping and scheduling of tasks and communications on a many-core SoC. The key idea is to decide the type of each communication between message passing and shared memory when we do the mapping and scheduling. By assigning a proper type to each communication, we can optimize the energy consumption, performance, or energy-delay product. To solve the optimization problem, the approach adopts a probabilistic algorithm coupled with some heuristics. To enhance throughput of the system, it performs software pipelined scheduling of the tasks using a modified iterative modulo scheduling technique. Experiments show that our algorithm achieves on average 50.1% lower energy consumption, 21.0% higher throughput, and 64.9% lower energy- delay product, compared to shared memory only communication.

In this paper, we present reconfigurable multiprocessor architecture for volume rendering. The multiprocessor consists of sixteen reconfigurable processors to exploit data parallelism of the volume rendering. Each processor has VLIW core and reconfigurable coarse-grained array specialized for control and data-intensive part of the program, respectively. The coarse-grained array can be configured dynamically, so that it can efficiently process different kernels of the volume rendering. The multiprocessor is implemented using verilog HDL and realized onto a commercial FPGA-based prototyping system. The experimental result shows that the presented multiprocessor has comparable performance to high-end desktop GPUs.

The latest biomedical applications require low energy consumption, high performance and wide energy-performance scalability to adapt to various working environments. This paper presents ULP-SRP, an energy efficient reconfigurable processor for the biomedical applications. ULP-SRP uses a Coarse Grained Reconfigurable Array (CGRA) for high performance data processing with low energy consumption. For the scalability, we propose three performance modes and Unified Memory Architecture (UMA). Energy optimization is accomplished by run-time mode switching along with automatic power gating. Experimental results show that ULP-SRP achieved 46.1% energy reduction compared to previous works.

Though Coarse Grained Reconfigurable Architecture (CGRA) is a flexible alternative for high performance computing, it has a crucial problem on instruction code whose size is so large that the instruction memory takes a significant portion of silicon area and power consumption. This article proposes an efficient dictionary-based compression method for the CGRA instruction code, where code bit-fields are rearranged and grouped together according to locality characteristics and the most efficient compression mode is selected for each group and kernel. The proposed method can reinstall the dictionary contents adaptively for each kernel. Experimental results show that the proposed method achieved an average compression ratio 0.56 in 4×4 array of function units for well-optimized applications.

This paper explores high-bandwidth data cache designs for a coarse-grained reconfigurable architecture processor family capable of achieving a high degree of instruction level parallelism. To meet stringent power, area and time-to-market constraints, we take an architectural approach rather than circuit-level multi-porting approaches. We closely examine two design choices: single-level banked cache (SLC) and two-level cache (TLC). A detailed simulation study using a set of microbenchmarks and industry-strength benchmarks finds that both SLC and TLC offer a reasonably competitive performance at a small implementation cost compared with a hypothetical cache with perfect ports and a multi-bank scratchpad memory.

In frame memory recompression, decompression latency consists of two components, i.e., memory access cycles for compressed data fetch, and decompression time. Compared to most earlier works which mainly focused on the compression ratio and, therefore, only reducing memory access cycles, this paper proposes a low-latency variable-length coding method called non-zero bit selection scheme (NBS). The proposed NBS enables highly parallel decompression achieving a three-cycle decompression for an 8×8 block, compared to previous methods requiring as many as twelve clock cycles for the case of exponential Golomb code. It is notable that the proposed NBS scheme has achieved this without deterioration of the compression ratio. Experimental result on a number of full HD videos shows that the compression ratio of the proposed method is at least not worse than that obtained with the exponential Golomb code on the average, while reducing the decompression time to 25% compared to the exponential Golomb code.

Reducing cache misses without increasing cache associativity is critical for reducing the power consumption and cache access time. This paper has focused on the stack of a program which often occupies more than half of total memory accesses (Calder, et. al., 1998). This paper, as a result, proposes so-called dynamic stack allocation where the stack pointer is shifted at run time to a memory location which is expected to cause least number of cache misses. We implemented the proposed scheme using so-called dynamic stack allocator (DSA) which consists of cache miss predictor (CMP) to compute cache miss probability based on least recently used (LRU) policy and stack pointer manager (SPM) to manage multiple stack locations. We also verified the proposed scheme with both FPGA and ASIC by using iNCITE and Dong-Bu electronics 0.18mum process, respectively. Experimental results show that dynamic stack allocation significantly reduces cache misses from 4% to 42% in various benchmarks with relatively small power consumption and no extra delay.

For system-level simulation of a complex system-on-chip design, multiple hardware simulators and emulators can be combined to work together. The simulation performance in this case is often limited by the communication overhead between simulators and emulators. To reduce the amount of communication in this heterogeneous simulation environment, we propose novel methods to find a time interval during which there are no transactions among simulators based on a dynamic prediction of transaction occurrence time for both software and hardware models. We also propose a simulator scheduling algorithm which allows the simulator to work alone without interaction with others when there is no transaction. By so doing, we reduced the amount of pure communication by a factor of 15 to 67 and, as a result, achieved a speed-up factor of 4 to 40 compared to existing lock-step simulation, as shown by experimental results with various application examples.

The paper presents a scheme for efficient channel usage between simulator and accelerator, where the accelerator models some RTL sub-blocks in the accelerator-based hardware/software co-simulation while the simulator runs a transaction-level model of the remaining part of the whole chip being verified. With conventional simulation, accelerator evaluations of simulator and accelerator alternate at every valid simulation time, which results in poor simulation performance due to the startup overhead of simulator-accelerator channel access. The startup overhead can be reduced by merging multiple transactions on the channel into a single burst traffic. We propose a predictive packetizing scheme for reducing channel traffic by merging as many transactions into a burst traffic as possible based on 'prediction and rollback'. Under ideal conditions with 100% prediction accuracy, the proposed method shows a performance gain of 1500% compared to the conventional one.