Daniel Tille

VLDB 2026 Research / reviewers in the wild / expert

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22ranked-venue papers

6as first author

10since 2021 · last 2026

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 22 · 6 first-author · 10 since 2021

Year	Publication	Venue	Position
2026	TDDB Stress Test Coverage Quantification using Cell-aware Transistor State Stress Model Vladimir A. Zivkovic, Stephan Eggersglüß, Andreas Glowatz, Daniel Tille	ETS	4
2025	Self-Aware Silicon: Enhancing Lifecycle Management with Intelligent Testing and Data Insights Fabian Vargas 0001, Marko S. Andjelkovic, Milos Krstic, Anirban Kar, Swati Deshwal, Yogesh Singh Chauhan, Hussam Amrouch, Daniel Tille, Sebastian Huhn 0001	ETS	8
2025	European Test Symposium Teams: an Anniversary Snapshot abstract The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing. Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi 0002, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. D. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard 0001, Marcello Traiola, Arnaud Virazel, Fernando Santos 0001, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Veiras Bolzani, Milos Krstic, Marko S. Andjelkovic, Fabian Vargas 0001, Grigor Tshagharyan, Gurgen Harutunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zainalabedin Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand	ETS	17
2025	Exploiting weak detections for optimizing pattern generation in Defect-Oriented Cell-Aware ATPG abstract As the industry advances towards smaller geometries for integrated circuits (ICs), internal cell defects have become increasingly crucial to address. Cell-Aware Testing (CAT) has emerged as the industry standard for achieving the high-quality levels required in modern ICs, as it explicitly targets intra-cell defects. However, the comprehensive defect coverage provided by CAT can result in a high test pattern count, which directly impacts test time and production costs.This paper proposes two complementary methodologies to optimize the cell library characterization phase by leveraging weak detections to maximize the number of Don’t Cares (DCs) and equivalent defects. The proposal produces an optimized Defect Detection Matrix (DDM) for the library, which is then used by the ATPG for pattern generation at the design level.The methodologies have been validated by running CAT ATPG for five different designs, using a 65nm cell library characterized with the proposed approach. The experimental results show that using the optimized DDMs reduces the number of patterns by an average of 8% and the pattern generation time by 11%, depending on the methodology used and the circuit analyzed. Alessandro Ciullo, Stephan Eggersglüß, Daniel Tille, Andreas Glowatz, Giusy Iaria, Paolo Bernardi 0002	ITC-Asia	3
2023	A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin abstract LBIST has been proven to be an effective measure for reaching functional safety goals for automotive microcontrollers. Due to a large variety of recent innovative features, every customer can adjust LBIST settings in a way that fits their use case. The downside of these user-defined configurations is the handling of their golden signatures: Traditionally, they can be computed only with access to the gate-level netlist. This is typically not possible for MCU customers because a netlist contains protected IP, which cannot be disclosed to third parties.This paper proposes a digital twin of the LBIST functionality that can overcome this drawback. It is an executable model that can be delivered together with the product. As a result, for the first time, a customer can compute a golden signature without knowledge of the netlist or other support of the supplier. We prove the efficacy of the digital twin in an industrial environment on an automotive microcontroller. Daniel Tille, Leon Klimasch, Sebastian Huhn 0001	VTS	1
2023	Performance Screening Using Functional Path Ring Oscillators abstract The testing of integrated circuits is an important topic, particularly in safety-critical applications. This is especially true for microcontrollers (MCUs) used in the automotive industry. A critical test is the performance screening in which the maximum clock frequency of the MCU is determined. For this performance screening, indirect monitors, such as ring oscillators (ROs), are used. This article presents a holistic overview of the functional path RO from the pre-silicon to the post-silicon. The implementation of such ROs is presented, as the associated advantages in terms of area consumption, leakage, and routing. In the post-silicon phase, the functional path RO frequencies are correlated with the MCU performance using machine learning approaches. Tobias Kilian, Daniel Tille, Martin Huch, Markus Hanel, Ulf Schlichtmann	IEEE Trans. Very Large Scale Integr. Syst.	2
2022	Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators abstract Automotive Microcontrollers (MCUs) are extensively tested to guarantee zero-defect quality. Performance screening is one of the critical factors to ensure that MCUs meet quality requirements. Ring Oscillator (RO) structures are used for this performance screening. Such RO structures usually cause routing overhead on the chip. The routing overhead increases, especially when many ROs are implemented. This paper presents a novel self-enabling technique that significantly reduces the routing overhead for functional path ROs. We present a proof of concept on a large automotive MCU. The routing overhead can be reduced by over 80% compared to traditional approaches. Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann	ETS	3
2022	A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data abstract A lot of effort and money is invested in testing to ensure zero-defect quality of automotive microcontrollers. One crucial test is the performance screening. Indirect structures such as Ring Oscillators (ROs) are used for this. Here, the quality of the performance screening strongly depends on the quality and selection of the RO structures used. This paper proposes a path selection and implementation method to provide a set of functional path ROs with good representativeness for the whole chip. In addition, a simulation-based validation is presented, which is used to improve the selection process continually. The proposed path selection is validated by simulation and on silicon. The results show a high diversity and good coverage of the chip parameters with the selected functional path ROs, providing good conditions for a high-quality performance screening. Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann	ITC	3
2021	A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators abstract The automotive industry sets high reliability standards for microcontroller (MCUs). To increase reliability, the automotive MCU manufacturers are looking for accurate performance screening. One of these performance screening mechanisms are functional path ring oscillators (RO). In this paper, a scalable and efficient method for creating functional path ring oscillators is presented. Implementation data demonstrate that functional path RO monitors show a significant advantage in area and power consumption over comparable performance screening methods. Tobias Kilian, Heiko Ahrens, Daniel Tille, Martin Huch, Ulf Schlichtmann	ITC	3
2021	Time and Area Optimized Testing of Automotive ICs abstract As cars become increasingly computerized and their safety functions evolve rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is rising dramatically with high-end models containing hundreds of embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive systems. This article presents a scan-based test scheme optimizing test time and area overhead during manufacturing and in-system test of automotive electronics. The proposed scheme deploys observation test points that capture the faulty effects in every shift cycle into separate observation scan chains. To reduce area overhead, the scheme enables the sharing of flip-flops among control points. It is also shown how test points enhance test coverage (TC) in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine TC are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in test quality over traditional solutions. Nilanjan Mukherjee 0001, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer	IEEE Trans. Very Large Scale Integr. Syst.	2
2019	Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns abstract This work presents a novel hybrid compression architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codeword-based compression scheme. The proposed architecture tackles the shortcomings of state-of-the-art techniques, which are widely to address the rising challenges of safety-critical applications enforcing a zero defect policy. Embedded test compression techniques had been introduced that allow the compression of a large share of the test patterns. However, depending on the test application (e.g. low pin count test) there is a certain number of test patterns, which are incompressible due to the architecture and will be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy. Therefore, the rejected test patterns are typically transferred in an uncompressed way bypassing the embedded compression, which is extremely costly. The proposed hybrid architecture mitigates the adverse impact of rejected test patterns on the compression ratio as well as on the test application time of state-of-the-art techniques. The experimental evaluation of industrial-sized designs clearly shows that a significant compression ratio up to 67.4 % and a test application time reduction up to 65.7% can be achieved. Sebastian Huhn 0001, Daniel Tille, Rolf Drechsler	ETS	2
2019	A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems abstract This work presents a novel hybrid compression architecture that seamlessly combines the advantages of an embedded test compression technique with a lightweight codeword-based compression scheme. Embedded test compression has proven to be beneficial and is widely used in industrial circuit designs. However, particularly, in test applications within low-pin-count environments, a certain number of test patterns is incompressible and will, therefore, be rejected. This leads to a test coverage decrease which, in turn, jeopardizes the zero defect policy of safety-critical applications like automotive microcontrollers. Therefore, the rejected test patterns are typically transferred in an uncompressed way bypassing the embedded compression, which is extremely costly. The proposed hybrid architecture mitigates the adverse impact of rejected test patterns on the compression ratio as well as on the test application time of state-of-the-art techniques. The experimental evaluation of industrial-sized designs clearly shows that a significant compression ratio up to 67.4% and a test application time reduction up to 72.9% can be achieved when utilizing the existing multi-channel interfaces. Sebastian Huhn 0001, Daniel Tille, Rolf Drechsler	ITC-Asia	2
2019	Test Time and Area Optimized BrST Scheme for Automotive ICs abstract As cars become increasingly computerized and their safety functions are evolving rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing more than a hundred embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. The paper presents a scan-based LBIST scheme optimizing test time and area overhead during in-system test applications for automotive ICs. It ensures highly reliable operations of ICs for the duration of their lifespan. The proposed scheme works with observation test points that capture faulty effects every shift cycle into separate observation scan chains. To reduce area overhead, the scheme takes advantage of a procedure allowing one to share flip-flops among control points. It is also shown how test points can enhance test coverage in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine observed faults are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in quality of test over traditional BIST schemes. Nilanjan Mukherjee 0001, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki	ITC	3
2018	On enabling diagnosis for 1-Pin Test fails in an industrial flow abstract The 1-Pin Test concept has proven to be beneficial for test cost reduction. By compacting test responses into a signature and reading them out at test end, test parallelism can be increased significantly. This reduces the test time and thus test cost. Especially cost-sensitive devices, e.g. IoT end nodes, profit. A drawback of this method is the limited capability of diagnosis due to the lack of cycle-accurate PASS/FAIL information. In this paper, we present a new approach to tackle this challenge. It enables the use of an industrial diagnosis flow for fails that occurred during 1-Pin Test. For this purpose, we propose failing vector and failing cycle analysis techniques. Our approach is fault model independent and not limited to a single fault assumption. We mitigate the aliasing problem by masking. The effectiveness of our approach is shown on an investigation of real silicon fails in industrial designs. Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut E. Graeb, Ulf Schlichtmann	ASP-DAC	1
2017	A lightweight X-masking scheme for IoT designs abstract The emerging Internet-of-Things (IoT) paradigm creates a new market for very small and cost-sensitive chips. Design costs must be as low as possible in order to be competitive. In this context, the 1-pin test has proven to be a beneficial way to significantly reduce test costs. However, the incorporated signature generation requires an X-free design, which is not always possible (e.g. due to timing exceptions in transition tests). Available X-masking approaches target large circuits and are therefore not suitable due to their large area overhead or because they require additional pins. In this paper, we present a solution to this business case problem. A new X-masking scheme with very small area overhead and the ability for usage during 1-pin test is proposed. We present experimental results on industrial designs. Those experiments show for the first time that transition tests with X-values in their response can be applied during 1-pin test. The method has been successfully verified on silicon and is already being applied during productive test application. Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen	ITC-Asia	1
2016	Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test abstract Launch-Switching-Activity (LSA) is a serious problem during at-speed testing of integrated circuits, since localized LSA may lead to severe IR-drop and thus failures. The excessive LSA is conventionally mitigated by reducing the switching activity through special low-power test generation techniques, typically resulting in severe test pattern inflation and high test costs. This work introduces a novel concept of Low-Capture-Power Test Points (LCP-TPs), which are inserted to reduce switching activity in critical High-Capture-Power (HCP) regions. LCP-TPs also help in retaining high test compaction capability. An optimization- SAT based procedure is proposed to compute a small set of optimal LCP-TP locations for compact at-speed test sets with effective capture power reduction. Experimental results clearly demonstrate the advantages of LCP-TP insertion. Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen	ATS	3
2010	Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs abstract It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially on large industrial circuits. These circuits usually contain a lot of functional redundancy which, on the one hand, is often needed during operational mode, but on the other hand, causes dispensable overhead during ATPG. Using the traditional circuit-to-CNF transformation, this redundancy is also contained in the SAT instances. The contribution of this paper is a new technique to improve the SAT instance generation for SAT-based ATPG. The objective of the proposed method is to use Binary Decision Diagrams (BDDs) to optimize the resulting CNF representations. In order to apply the proposed technique to industrial circuits, we developed dedicated BDD operations using a multiple-valued logic. The experimental results, obtained on large industrial designs, show that the accomplished optimizations result in a considerable acceleration of the overall ATPG runtime as well as in a significant reduction of the unclassified faults. Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler	ETS	1
2010	Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation abstract The influence of crosstalk noise grows as the feature sizes in modern designs decrease. Crosstalk-induced effects are able to cause major timing violations, especially if multiple aggressors affect certain lines. However, conventional Automatic Test Pattern Generation (ATPG) algorithms for delay test do not consider these effects during test generation. This increases the possibility that chips which passed the testing phase might fail due to crosstalk-induced effects. In this paper, we propose a new efficient ATPG approach for generating delay tests considering crosstalk-induced effects using Boolean Satisfiability (SAT). Previous approaches used a two-step procedure to increase the crosstalk-induced noise. As a result, the search space is highly restricted. In contrast, the proposed approach is able to do test generation and excite multiple aggressors in one step. By this, more aggressor combinations can be found and the generated test potentially induce more crosstalk noise on the victim. In order to maximize the crosstalk-induced effects of the test, an exact branch-and-bound algorithm and a static aggressor ordering heuristic are applied and compared. Experimental results demonstrate the efficiency and effectiveness of the approach. Stephan Eggersglüß, Daniel Tille, Rolf Drechsler	ISCAS	2
2010	Incremental Solving Techniques for SAT-based ATPG abstract Automatic test pattern generation (ATPG) based on the Boolean satisfiability (SAT) problem has recently been proven to be a beneficial complement to traditional methods. Efficient SAT techniques yield a robust fault classification. In this paper, we present methodologies to improve the efficiency of SAT-based ATPG. First, we give a detailed run time analysis of a state-of-the-art SAT-based ATPG tool. By only taking circuit partitions into account and applying incremental SAT solving, both SAT instance generation and SAT instance solving can be accelerated and the robustness of the ATPG process is increased. Besides the significant run time reduction of SAT-based ATPG, the methodology can additionally be used to improve the test set quality. The proposed techniques are applied for the stuck-at and for the transition fault model. A set of large industrial designs is used to show the efficiency of the approach. Daniel Tille, Stephan Eggersglüß, Rolf Drechsler	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1
2009	Speeding up SAT-Based ATPG Using Dynamic Clause Activation abstract SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduced using a SAT-based ATPG approach. In contrast to structural ATPG, SAT solvers work on a Boolean formula in conjunctive normal form (CNF). This results in some disadvantages for SAT solvers when applied to ATPG, e.g. CNF transformation time and loss of structural knowledge. As a result, SAT-based ATPG algorithms are very robust for hard-to-test faults, but suffer from the overhead for easy-to-test faults. We propose the SAT technique dynamic clause activation (DCA) in order to reduce the run time gap between structural and SAT-based ATPG algorithms and, at the same time, retain the high level of robustness. Using DCA, the SAT solver works on a partial formula of a logic circuit which is dynamically extended during the search process using structural knowledge. Furthermore, efficient dynamic learning techniques can be easily integrated within the proposed technique. The approach is evaluated on large industrial circuits. Stephan Eggersglüß, Daniel Tille, Rolf Drechsler	Asian Test Symposium	2
2009	A fast untestability proof for SAT-based ATPG abstract Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. SAT solvers work on instances given in Conjunctive Normal Form (CNF). The required transformation of the ATPG problem into CNF is one main part of SAT-based ATPG and needs a significant portion of the overall run time. Solving the SAT instance is the other main part. Here, the time needed is often negligible - especially for easy-to-classify untestable faults. This paper presents a preprocessing technique that speeds up the classification of untestable faults by accelerating the SAT instance generation. This increases the robustness of the entire ATPG process. The efficiency of the proposed method is shown by experiments on large industrial designs. Daniel Tille, Rolf Drechsler	DDECS	1
2008	On Acceleration of SAT-Based ATPG for Industrial Designs abstract Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has to be transformed. During transformation, relevant information about the problem might get lost and, therefore, is not available in the solving process. In this paper, we present a technique that applies structural knowledge about the circuit during the transformation. As a result, the size of the problem instances decreases, as well as the run time of the ATPG process. The technique was implemented, and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. It is shown that the overall performance of an industrial framework can significantly be improved. Further experiments show the benefits with regard to the efficiency and robustness of the combined approach. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	7