This paper presents a low-power CMOS interface for magnetic tunnel junction-based vortex oscillator (MTJ-VO) devices, suitable for neuromorphic networks. In the proposed approach, a rectified linear unit (ReLU)-like function is implemented by exploiting the dependence of the MTJ-VO frequency on its bias current (MTJ-ReLU). Compared with prior works, the proposed MTJ-VO-based neuron offers the distinct advantage of directly connecting multiple neurons to realize more complex neural networks. The CMOS interface was designed and verified through transistor-level simulations in a 65 nm CMOS technology using MTJ-VO data obtained from device measurements. Finally, the functionality of the MTJ-ReLU neuron was validated by implementing a 784×256×10 artificial neural network (ANN), achieving a test accuracy of 94%.

This paper presents the design of an ultra-low power relaxation oscillator for Internet-of-Things (IoT) power management applications. The new design employs a dual-comparator architecture with a novel dynamic biasing technique to minimize power consumption. The biasing of both comparators is dynamically regulated to ensure their operation only during decision-making events, substantially reducing power consumption. The proposed oscillator achieves a power consumption of only 74.6nW at a stable frequency of 1.2kHz, exhibiting a standard deviation of merely 74Hz. The new design demonstrates a 73% reduction in power compared to the conventional design. The circuit is simulated in a 65nm, 1.2V CMOS process, with all results verified by post-layout simulation.

Low power, long range, wireless communication technologies enable a range of monitoring applications in difficult to reach locations. In this paper, we investigate one such application for monitoring an underground pipeline infrastructure in the 868MHz Industrial, Scientific and Medical (ISM) band. We deployed five underground LoRa/LoRaWAN communication modules on district heating pipes, sealed off below an asphalted road segment. Several specific measurements have been conducted to characterize the propagation conditions from below to above ground, and from which we propose models decomposing propagation into separate contributions from soil, ground to free-space, and above ground propagation. The main novelty of the work lies in the application to covered surfaces and the combined above ground/aerial model framework for communication from below ground. It was found that the Peplinski soil loss model is applicable for estimating the effect of the ground, which in combination with Fresnel refraction and a log-distance model for above ground propagation leads to a consistent modeling framework for propagation to lamp post height gateway infrastructure. For aerial-based gateways, the main finding is that the propagation from below to above ground changes the propagation behavior with distance above ground, despite the otherwise unobstructed free space propagation path. This led to a path loss model with loss increasing exponentially with height and according to cylindrical wave propagation with lateral (2D) distance, aligning with the estimations based on the ground-based model. The results suggest overall that the volumetric water content (VWC) of a compacted and covered soil mixture tends to stabilize to high values.

This paper presents the design and implementation of a miniaturized, low-noise Magnetic Tunnel Junction (MTJ)-based proximity sensor with a high-performance readout channel. The MTJ-based proximity sensor consists of 1102 circular pillars of 100um diameter arranged in series, providing accurate detection of subtle interactions, such as a finger approaching the sensor. The system exhibits a 54 dB gain and a bandwidth of 1 kHz, with a noise power density of less than 30 nV/√Hz at 100 Hz, ensuring high precision. The proximity sensor demonstrated linear behavior for distances from 18 mm to 45 mm, with a sensitivity sufficient to detect low magnetic field variations. Experimental validation of the sensor shows a high degree of accuracy (R2= 0.9715), confirming its potential for use in touchless control, mobile technology, and industrial applications.

In this work, we introduce the Spike Count Deviation (SCD) algorithm for use with spike-encoded electromechanical impedance (EMI) data, aimed at enhancing on-edge structural health monitoring (SHM) systems. The proposed approach achieves significant data compression without compromising accuracy. We apply step-forward spike encoding alongside the SCD algorithm to two reinforced concrete samples under five simulated damage scenarios. Experiments show a damage detection accuracy of 99.53%, with an average of 350 generated binary spikes.The performance of the proposed approach is compared to two studies using the conventional Root Mean Square Deviation (RMSD) algorithm for damage detection. We demonstrate a comparable detection accuracy of >99% and show that the SCD algorithm is resistant to temperature effects, exhibiting 10 times greater sensitivity to damage than to temperature variations.

This paper presents a novel approach to reservoir computing (RC) using Granular Vortex-Based Magnetic Tunnel Junctions (GV-MTJs) for temporal applications. GV-MTJs, with their unique magnetic domain configurations and granular structures, provide the necessary fading memory and non-linear dynamics essential for RC. The vortex core’s oscillatory motion within the device allows for temporal correlation of inputs, giving fading memory, while grain-induced non-linear resistance and frequency variations enhance data dimensionality. Our findings indicate that varying device parameters can affect the relaxation time and gyrotropic frequency in both simulation and experiments. Relaxation times range from 100-140 ns and frequencies from 250-100 MHz. Through experiments, the classification error was reduced by 27% for the best sample, others showed limited potential. Due to signal application speed constraints, the fading memory is not fully utilized. However, the inherent RC capabilities of GV-MTJs are validated. This paper highlights the promise of GV-MTJs in neuromorphic computing and suggests avenues for future research to optimise their use in practical applications.

This article presents a low-power fully CMOS temperature sensor in a 65 nm process, suitable for monitoring the battery-powered application-specific integrated circuit (ASIC) designs. The circuit converts a proportional-to-absolute-temperature (PTAT) current to a complementary-to-absolute-temperature (CTAT) binary code using a low-power time-to-digital converter to-digital converter (TDC). To enhance conversion efficiency, we introduce a two-stage dynamic comparator that consumes 40% less power than conventional designs by enabling the preamplifier only when precise detection of the integration stop time is required. The 0.16$\text{mm}^{2}$prototype consumes only 0.97 nJ/conversion, achieving a resolution figure of merit (FoM) of 0.018 nJ$\cdot $$\text{K}^{2}$. Measurements show an inaccuracy of$\pm 0.85~^{\circ }$C ($3\sigma $) over a temperature range of –$20~^{\circ }$C to$+ 120~^{\circ }$C.

This paper presents a chopper-stabilized three-stage operational amplifier (OpAmp) with a unity gain bandwidth of 69 MHz and an input referred noise density of 3 nV$/\surd{Hz}$. The proposed design achieves a stable unity gain by proposing a new pole and zero scheme with very low power consumption, drawing only 3.3 mA from a 1.8 V power supply while driving a load capacitor as large as 100pF. To achieve rail-to-rail input swing, the design uses both NMOS and PMOS differential pairs at the input and biases them in the subthreshold region to provide an identical net trans-conductance over the rail-to-rail input common mode. Furthermore, an adaptive biasing is employed and the current sources are kept ON during large signal transitions at the input, thus eliminating crossover distortion and providing a high slew rate of 40 V/$\mu$s at a 100 pF load capacitor. The design employs chopping at 2.5 MHz and is enhanced with a local ripple reduction loop, making the OpAmp suitable for high gain and wide bandwidth applications with less filtering required. The design also reduces the input bias current significantly from 500 nA to 1.5 nA by buffering the input and applying it to the modified bootstrap switches. The proposed OpAmp, fabricated in a 0.18$\mu$m CMOS process, exhibits a maximum offset of 4.5$\mu$V, a flicker noise corner frequency of 246 Hz, a DC gain of 146 dB, a power supply rejection ratio of 123 dB, and a common mode rejection ratio of 116 dB.

With the rapidly evolving internet of things (IoT) era, the ever-rising demand for data transfer and storage has put a knotty problem on conventional computers, known as the von Neumann bottleneck and memory wall problem. Slow scaling of CMOS transistors due to physical and economical limitations further exacerbates the situation. It is only logical to mimic what has been known so far as the most energy-efficient system, the human brain. The brain-inspired neuromorphic computing systems compute and store the data locally, which dramatically reduces area and energy consumption. In this work, we demonstrate thermal-induced multi-state memristors for neuromorphic engineering applications. We show that in a neural network that uses a memristor-spintronic nano oscillator connection to implement the synapse-neuron pair, with increased temperature, the total power consumption could be reduced by more than 50 % without degrading the output power of a spintronic-based neuron.

Many classification applications rely on real-time processing and detection of RF signals at high frequencies. RF signal sampling requires sophisticated hardware, i.e., broadband analog front-ends and high-speed analog-to-digital converters according to the well-known Shannon-Nyquist theorem. Such devices either are expensive or suffer from limited detection bandwidths and sampling rates. Here, we proposed a novel spintronic-based classification front-end for real-time analysis and classification of RF signals. In comparison to the conventional CMOS-based systems, the proposed system can increase the classification speed dramatically while consuming an order of magnitude less power.

Spiking neural networks (SNNs) are envisioned to be a better alternative to artificial neural networks (ANNs) for targeted applications. Multi-core implementation of SNNs has been built to achieve a resource-efficient design. However, managing the spike traffic congestion while routing the spikes between different cores requires a performance-resource tradeoff to avoid any packet loss. This paper presents a novel router architecture servicing ongoing packets in a 2-D mesh network while guaranteeing no packet drop. Here, the packets are distributed across different paths to reduce spike traffic. The proposed router suitable for a$16\times 16$network occupies an area of 0.001mm2 in 28nm CMOS technology, while consuming 75 fJ/transmission.

In this paper, a 3-bit hybrid spin-CMOS Flash analog to digital converter (ADC) is developed, which works based on switching of perpendicular-anisotropy magnetic tunnel junctions (p-MTJs) using both spin Hall effect (SHE) and spin-transfer torque (STT). The structure consists of unconnected p-MTJs in which heavy metals (HMs) are implemented with different cross-sectional areas leading to devices with different critical current (IC) values. ICvalues act as reference currents (Iref) eliminating the need for transistors with different sizes creating various values of Iref. Moreover, the power-hungry comparators in complementary metal-oxide-semiconductor (CMOS) Flash ADC can be replaced with p-MTJs because they compare the input current (Iin) with their IC. Hence, this approach can reduce the chip area and the mismatch issue as compared to the conventional CMOS Flash ADC. In this structure, a copy of Iin passes through the HM of each p-MTJ, which improves the tunnel magnetoresistance (TMR) and as a results increasing the reading reliability, linearity, and speed of spin Hall-based ADCs with attached HMs. The simulation results in 180nm CMOS technology show 845 μW of power consumption at 200 MS/s with the differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.149 LSB (least significant bit) and 0.085 LSB, respectively.

Neuromorphic computing could pave the way to a new generation of smart sensors that can process signals locally through Spiking Neural Networks (SNNs). For this paradigm to take hold, it is necessary to have an analog-to-spike encoder adaptable to a wide range of applications. The encoding system should offer the possibility to try different encoding algorithms, giving freedom to the designers to select the most appropriate approach for the target task. At the same time, it should feature a tunable parameter to modulate the spike density, in the pursuit of a compromise between accuracy and power consumption. Therefore, the goal of this work is to provide a platform enabling the conversion of analog signals to a sequence of spikes, characterized by flexibility, high energy efficiency, and small area. We introduce an encoder designed and simulated in a standard 0.18 μ-m CMOS process which benefits from a switch- capacitor and a dynamic comparator to achieve very high energy efficiency. The controller unit can switch between Slope-based or Step-Forward Encoding algorithms. The encoder consumes 30 fJ/spike at 1.5 V supply voltage and occupies an area of 0.00325 mm2.

This paper proposes a novel system for ultrasonically-power optogenetic microstimulator. In this system, a novel powering approach for the comparators is proposed that improves the power conversion efficiency of the rectifier. This is done by lowering the Rail-to-Rail supply voltage of the comparators and consequently their propagation delay. This technique enhances the power conversion efficiency of the active rectifiers in two ways: a. decreasing the propagation delay of the comparators; and b. enabling reuse of consumed power by the comparators and drivers of power transistors. The proposed system including the active rectifier, a novel double-pass regulator, a current reference, and a burst detection circuit is simulated in TSMC 0.18-μm CMOS technology and occupies an area of 0.09 mm2. The proposed active rectifier connected to a load of 3 kΩ, generates an output voltage of up to 3 V out of an input AC signal with the amplitude of 3.2V and the frequency range of 1-14 MHz. In the same frequency range and with the same load, it exhibits a voltage conversion ratio of 92.25-93.75% and power conversion efficiency of up to 95%. The double-pass regulator is proposed for seeking both power efficiency and over-voltage protection in this specific design.

In this paper, we propose two independent gate (IG) FinFET SRAM cells that use PMOS access transistors and back-gate (BG) biasing to achieve a high-stability performance. In the first cell, the back-gate of the access transistors is connected to the adjacent storage nodes, and the back-gate of the pull-down transistors is dynamically biased. Simulations indicate that the first proposed cell offers higher read static noise-margin (SNM), higher write-ability, least static/dynamic power, and a comparable read current compared to the previous IG-6TSRAMs. The second cell is a novel independently-controlled-gate FinFET SRAM cell, which provides a high read stability, the highest write-ability, low static power dissipation and high read current compared to the previously reported independently-controlled-gate FinFET SchmitTrigger based SRAM cells. This cell supportsbit-interleaving property at VDD = 0.4 V with high read/write yields.

This paper presents a novel low-power Tunneling Field-Effect-Transistor (TFET) 8T-SRAM cell. The proposed cell uses a supply feedback to improve its stability. The new structure at the supply voltage of 300 mV, compared to the conventional 6T SRAM, shows 33% and 26% improvements in Read Static Noise Margin (RSNM), and write margin (WM), respectively. Layout drawn in 32-nm technology shows that the proposed 8T cell offers 1.2X larger area overhead compared to the conventional 6T cell, however with considering of higher performance and stability of the proposed design at low supply voltages, this is worthy of use. Also, proposed design shows better performance under process variations compared to the 8T-SRAM cell designed using other technologies.

A high slew rate operational transconductance amplifier (OTA) based on the dynamic current boosting paths is presented. Two flipped voltage-follower (FVF) cells adaptively bias the input drivers and provide a class AB operation with capability of adding new input to output paths. In addition to the reduction of the settling time of the step response, these paths operate as new drivers that increase the small signal transconductance of the proposed amplifier. Simulation results in a TSMC 90 nm complementary metal oxide semiconductor (CMOS) technology show an 83 % decrease in the settling time and a 14.5 dB increase in the DC gain of the proposed class AB amplifier versus the conventional class A amplifier.

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising candidate for next-generation computing systems. However, with increasing process variation and decreasing supply voltage, a big design challenge of embedded STT-MRAMs is to guarantee negligible read-disturbance and high yield. In this paper, to deal with the read reliability challenge, a sensing circuit with strong positive feedback and a high sensing margin is proposed. It improves the sensing margin (SM) by 10.42×/3.3× and a with 1.24×/1.59× lower read energy at iso-sensing time (2ns) in comparison with the conventional sensing scheme and the state-of-the art current-sampling-based sensing circuit. Moreover the proposed scheme supports six sigma and higher yield for both states 0 and 1, while the compared schems fail.

This paper presents a spin-orbit torque magnetic random access memory (SOT-MRAM) using perpendicular-anisotropy magnetic tunnel junction (p-MTJ). In spite of conventional p-MTJ based SOT-MRAMs which need an external magnetic field to achieve a deterministic switching, the proposed cell uses a spin-torque transfer (STT) current where we show that the cell needs only two access transistors. This can solve the thermal instability, complexity and process variation sensitivity issues of the conventional SOT-MRAMs. In addition, it maintains the advantage of conventional p-MTJ based SOT-MRAMs such as ultra-fast switching and enhanced reliability of the MTJ. Our simulation results show that the proposed SOT-MRAM can achieve 3.3X and 2.8X faster and energy efficient write operation in comparison with the conventional SOT-MRAMs.

Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future nonvolatile memories. It advantages the benefits of current state-of-the-art memories including high-speed read operation (of static RAM), high density (of dynamic RAM), and nonvolatility (of flash memories). However, the write operation in the 1T-1MTJ STT-RAM bitcell is asymmetric and stochastic, which leads to high energy consumption and long latency. In this paper, a new write assist technique is proposed to terminate the write operation immediately after switching takes place in the magnetic tunneling junction (MTJ). As a result, both the write time and write energy consumption of 1T-1MTJ bitcells improves. Moreover, the proposed write assist technique leads to an error-free write operation. The simulation results using a 65-nm CMOS access transistor and a 40-nm MTJ technology confirm that the proposed write assist technique results in three orders of magnitude improvement in bit error rate compared with the best existing techniques. Moreover, the proposed write assist technique leads to 81% energy saving compared with a cell without write assist and adds only 9.6% area overhead to a 16-kbit STT-RAM array.

In this paper, a low-power electroencephalogram (EEG) analog front-end (AFE) with ultra-high input impedance is presented. This AFE can be utilized for both dry and non-contact biomedical applications due to its very high input impedance along with DC signal suppression. The amplifier achieves an input impedance of 45 fF ∥1 TΩ and a common mode rejection ratio (CMRR) higher than 110 dB. The power consumption of the proposed 8-channel AFE and its input referred noise over the 0.5-100 Hz bandwidth are 1.62 μW and 2.62 μVrms, respectively. This yields a noise efficiency factor (NEF) of 3.11. The simulations are carried out in the 180 nm standard CMOS technology using a ± 0.5 V power supply.

This paper presents a low-power instrumentational amplifier (IA) design for EEG signal acquisition for seizure detection. The proposed structure provides a power per channel of 0.92 μW at supply voltage of 0.8 V. Due to the use of buffer structures and impedance boosting loops in the proposed design, the input impedance has reached up to 160 GΩ and 16 GΩ at 1 Hz and 10 Hz frequencies, respectively. Also, the use of design and chopping techniques will lead to an input-referred noise of 1.7 μVrms over the bandwidth of 0.5-100 Hz with a noise efficiency factor (NEF) of 3.87 and a CMRR of 137 dB. The simulations are done using TSMC 180 nm CMOS technology at the supply voltage of 0.8 V.

In this brief, a new write assist technique is proposed to improve the write characteristics of 1T-1 magnetic tunnel junction (MTJ) spin-torque transfer memory bitcell through a symmetric write operation. This is done by applying a negative voltage to the bitline during write 1 operation. The proposed technique is compared with the best previously proposed techniques. The simulation results using 65-nm CMOS technology show that the proposed write assist technique results in 19% improvement in write energy compared with the boosted wordline (BWL) technique. In addition, the proposed write assist technique leads to 12% and 48% bitcell area reduction compared with BWL and balanced write techniques, respectively. Furthermore, the maximum voltage across the MTJ is reduced by 20% and 6% compared with BWL and balanced write techniques, respectively.

Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future non-volatile memories. However, the write operation in 1T-1MTJ STT-RAM bit-cells is asymmetric and stochastic which leads to high energy consumption and long latency. In this paper, a new write assist technique is proposed to terminate the write operation immediately after switching takes place in the MTJ. As a result, both write time and write power of 1T-1MTJ bit-cells improve. Moreover, the proposed write assist technique is robust in the presence of process variations. Simulation results using 65nm CMOS access transistor and 40-nm magnetic tunneling junction technology confirm that the proposed write assist technique results in three orders of magnitude improvement in bit error rate compared with the best existing techniques. Moreover, the proposed write assist technique leads to 81% power savings compared with a cell without write assist.

This paper presents a novel subthreshold 8T-SRAM for ultra-low power applications. The proposed SRAM cell improves write margin by at least 22% to the standard 6T-SRAM cell at supply voltage of 1V compared. Furthermore, read static noise margin is improved by at least 2.2X compared to the standard 6T-SRAM cell. Although by the use of the proposed SRAM cell, the total leakage power is increased for superthreshold regions, the proposed cell is able to work at supply voltages lower than 200mV with significantly improved robustness without any leakage increase. The proposed SRAM design improves write margin of the SRAM cell in comparison to the standard 7T-SRAM cell. The proposed circuit is designed in TSMC 65nm CMOS technology.

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.

In this paper, we present a model for estimating the performance of a team of agents, based on the capabilities of the agents and importance of these capabilities for the task. Performance of a team is assumed to be the sum of contributions of individual agents and contributions of subgroups built in the team. We introduce a set of notations, which is required for discussing the suggested models. We also propose a model to estimate the benefit of an agent from interaction with other agents in a subgroup. Based on this benefit model and different (common) strategies, the agents devise plans in which they formulate to what extent they are willing to cooperate with other agents. A negotiation algorithm that resolves the conflicts between the desires of the agents is presented. The effect of this algorithm and different strategies are tested on a set of generated data. The test results show that the performance of a team when the agents choose a cooperation strategy that follows the principle of least effort (Zipf's law) is higher than teams with other cooperation strategies.

A fully differential rail-to-rail Operational Transconductance Amplifier (OTA) with improved DC-gain and reduced power consumption is proposed in this paper. By using the adaptive biasing circuit and two differential inputs, a low stand-by current can be obtained together with reduced power consumption. The DC-gain of the proposed OTA is improved by adding a partial feedback loop. A Common-Mode Feedback (CMFB) circuit is required for fully differential rail-to-rail operation. Simulations show that the OTA topology has a low stand-by power consumption of 96μW and a high FoM of 3.84 [(V/μs.pF)/μW] for a load capacitor of 10pF.

In this paper we describe decision support and simulation techniques to facilitate effects-based planning. By using a decision support tool, a decision maker is able to test a number of feasible plans against possible courses of events and decide which of those plans is capable of achieving the desired military end state. The purpose is to evaluate plans and understand their consequences through simulating the events and producing outcomes which result from making alternative decisions. Plans are described in the effects-based approach to operations concept as a set of effects and activities that together will lead to a desired military end state. For each activity we may have several different alternatives. Together they make up all alternative plans, as an activity tree that may be simulated. Simulated plans that are similar in both their structure and consequence are clustered together by a Potts spin neural clustering method. These plans make up a robust set of similar plans that function as ready alternatives should dynamic replanning be necessary as the situation evolves.

Base Object Model (BOM) is a component-based standard designed to support reusability and Composability. Reusability helps in reducing time and cost of the development of a simulation process. Composing predefined components such as BOMs is a well known approach to achieve reusability. However, there is a need for a matching mechanism to identify whether a set of components are composable or not. Although BOM provides good model representation, it lacks capability to express semantic and behavioral matching.In this paper we propose an approach for matching behavior of BOM components by matching their statemachines. Our proposed process includes a static and a dynamic matching phase. In the static matching phase, we apply a set of rules to validate the structure of statemachines. In the dynamic matching phase, we execute the statemachines together at an abstract level on our proposed execution framework. We have developed this framework using the State Chart Extensible Markup Language (SCXML), which is a W3C compliant standard. If the execution terminates successfully (i.e. reaches specified final states) we conclude that there is a positive match and the behavior of these BOMs is composable. We describe the matching process and the implementation of our runtime environment in detail and present a case study as proof of concept.

A new current-mirror sense-amplifier based flip-flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed flip-flop at ultra-low voltage (down to 120 mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the pulse generator stage as well as the delay of the set-reset (SR) latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed flip-flop is implemented in a 65 nm CMOS technology.

In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65 nm standard models are used for simulations.

Creating simulation models via composition of predefined and reusable components is an efficient way of reducing costs and time associated with the simulation model development process. However, in order to successfully compose models one has to solve the issues of syntactic and semantic composability of components. HLA is the most widely used architecture for distributed simulations today. It provides a simulation environment and standards for specifying simulation parts and interactions between simulation parts. But it provides little support for semantic composability. The Base Object Model (BOM) standard is an attempt to ease reusability and composition of simulation models. However, BOMs do not contain sufficient information for defining concepts and terms in order to avoid ambiguity, and provide no methods for matching conceptual models (state machines). In this paper, we present our approach for enhancement of the semantic contents of BOMs and propose a three-layer model for syntactic and semantic matching of BOMs. The semantic enhancement includes ontologies for entities, event and interactions in each component. We also present an OWL-S description for each component including the statemachines. The three-layer model consists of syntactic matching, static semantic matching and dynamic semantic matching utilising a set of rules for reasoning about the compositions. We also describe our discovery and matching rules, which have been implemented in the Jess inference engine. In order to test our approach we have defined some simulation scenarios and implemented BOMs as building blocks for development of those scenarios, one of which has been presented in this paper. Our result shows that the three-layer model is promising and can improve and simplify composition of BOM-based components.

Development of simulation models is a multi-disciplinary and time/resource consuming process. An approach to reduce the associated costs and improving the usability of the models is to compose simulation models through reuse of predefined and already existing, validated simulation components. Using this method the simulation model is built in a component-based fashion. The Base Object Model, BOM, is a new standard for defining reusable and composable simulation components. The introduction of BOMs into the simulation community opens up the possibility of component based simulation development approach that is faster and more efficient than today's simulation creation process. In this paper we describe a process that has been developed at the Swedish Defence Research Agency (FOI) with the aim to speed up and improve the development of simulation models. This process utilizes the BOM concept coupled with ontologies in simulation development, and employs SRML (Simulation Reference Markup Language) as a means to define a component based simulation on a high-level. We present our experimental results and findings based on our implementation of the proposed process. Our experience indicates that including ontological information in BOMs will further increase their usability

Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in and high-speed applications in ultra deep submicron technologies. The proposed circuit employs a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. According to simulations in a predictive 70nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention between keeper transistor and NMOS evaluation transistors at the beginning of evaluation phase. This results in less power dissipation for the proposed technique.

The high level architecture (HLA) is widely used in defense applications as a common framework for modeling and simulation. The federation development and execution process (FEDEP) is a generalized process to build HLA federations from scratch. However, simulation model design, implementation, testing and execution defined in the FEDEP are time consuming and expensive. The model construction environment (MCE) is introduced in this paper as a Web-based system to enhance the efficiency of the federation development by reusing the existing simulation object models (SOM) to build new federation object models (FOM). To ensure the compatibility of the SOMs in a FOM, a matching algorithm is defined and tested. An extensible elements scheme is designed to help shape the characteristics of the FOM/SOMs. This study can contribute to more cost-efficient methodologies for the development and execution of simulation models.

The Data Distribution Management (DDM) service in the runtime infrastructure of high level architecture is employed to reduce the amount of irrelevant data communicated between federates and cut network communication cost. Current DDM schemes include mainly region-based and grid-based filtering mechanisms. We propose an agent-based DDM filtering mechanism to use agents to perform accurate data filtering in DDM. The agent-based DDM is supposed to filter out all the irrelevant information and route only the information that subscribers want. In this paper, an agent-based DDM mechanism is developed and incorporated into the runtime infrastructure. The efficiencies of the agent-based filtering mechanism and the other two traditional mechanisms are compared in an AWACS sensing aircraft experiment scenario. The results show that agent-based filtering mechanism communicates only the exactly relevant data and minimizes the network communication cost.