The performance of gigascale integration chips improves by cryogenic technologies such as subambient cooling. In these conditions, interconnects may perform at temperatures as low as 50 K. However, the local temperature of interconnects could easily be as high as 600 K at high-temperature chips. In this brief, we investigated the impact of temperature on delay of local, intermediate, and global interconnects of International Technology Roadmap for Semiconductors Node 2024. This is done for different values of interconnect width and length, nanotube diameter, and percentage of metallic carbon nanotubes (CNTs) in a grown bundle. Results are compared with those of copper counterpart. We showed that for local layers, a bundle of single-walled CNTs (BSWNTs) interconnects could outperform copper interconnects up to 17%, 35%, and 44%, respectively, at 50, 300, and 600 K, whereas for intermediate and global layers, there is a negligible difference between delay of copper and BSWNT interconnects at all temperatures.

Cryogenic technologies not only improve the performance of interconnects but also the performance of transistors and consequently drivers and repeaters. Although in cryogenically cooled integrated circuits the local temperature of interconnects and transistors may be as low as 50 K, it may easily reach to 600 K in high-temperature chips. In this brief, we investigated the impact of temperature on the delay of local, intermediate, unit-repeater-inserted (URI), and cascaded repeater-inserted (CRI) global copper interconnects for minimum technology node with available transistor model (32-nm technology). Our results show that temperature variation of driver resistance could change the delay of local and intermediate interconnects, respectively, down to -33% and -28% at low temperatures, and up to +240% and 232% at high temperatures relative to the room temperature delay. Moreover, while the contribution of temperature dependency of interconnect is negligible for local and intermediate layers, the temperature dependency of repeater and interconnect could vary the delay of URI and CRI global layer interconnect down to -23% and -38% at low temperatures, and up to +116% and +200% at high temperatures, respectively.

In this paper, n-tier methodology is developed to design multilevel interconnect architecture of macrocells using single-wall carbon nanotube (SWCNT) bundles. Upper limit of low-bias voltage of SWCNT bundle interconnects is derived and its dependence on temperature, SWCNTs' diameter, and interconnect length is studied. Possibility of using SWCNT bundles as local interconnects at 7.5-nm technology node is discussed, and it is shown that SWCNT bundles with 1 nm diameter cannot be used at the first interconnect metal level. Using Cu and SWCNT bundles, multilevel interconnect architecture of a 7.5-nm ASIC macrocell is designed which reduces the number of metal levels by 27% and power dissipation by 25% compared with the multilevel interconnect architecture designed with only Cu. The effect of aspect ratio (AR) on the n-tier design is studied. It is shown that decreasing AR of SWCNT bundle interconnects, decreases total power dissipation of the ASIC macrocell by 41%. The impact of temperature variation on the design of multilevel interconnect architecture is also investigated.

In this brief, we use the alpha power law model for MOS devices to reach a more accurate modeling of CMOS buffers in very deep submicrometer technologies. We derive alpha model parameters of a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICE simulations. By analytical efforts we find the output resistance of a minimum-size buffer and compare it with those extracted from HSPICE simulations. We propose a new model for the output resistance of a given-size buffer in any technology, which demonstrates 3% error on average as opposed to the conventional model. Also a new buffer resistance is proposed analytically and numerically to calculate the crosstalk for interconnect analysis applications. In addition, we propose a model for the transfer function zero generated by the gate-drain capacitances of MOS transistors, which cause the overshooting effect, and develop an accurate expression for modeling this phenomenon. As the final point, together with the input-to-output capacitance, the equivalent output resistors present a simple and accurate macromodel for the CMOS buffer.

Based on physical circuit models the performances of signal and power interconnects at the local, semi-global and global levels are modeled at 100degC. For local signal interconnects, replacing copper wires with a typical aspect ratio of 2 by thin SWNT interconnects can lower power dissipation by 50%. This would also improve their speed by up to 50% by the end of the ITRS. Copper wires and large diameter MWNTs offer the lowest resistance for power distribution in the first and second interconnect levels, respectively. SWNT-bundles and MWNTs can be used to lower the delay of signal interconnects in semi-global levels. MWNTs with diameters of 50 nm and 100 nm can potentially increase the bandwidth density of global interconnects by up to 50% and 100%, respectively.

Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and die size for circuit blocks or logic cores of microchips. It includes a methodology for co-optimization of signal, power and clock interconnects, and a newly derived stochastic wiring distribution that gives reduced error than prior work when compared to measured data. Results of IntSim are found to match well with actual data from an analyzed microprocessor. Several case studies are conducted to show this CAD tool’s utility as a system level simulator: (i) Wire resistivity increases due to size effects are projected to increase die size of a 22nm low power logic core by 30% and power by 7%. (ii) When compared to a 22nm low power logic core with copper interconnects, a similar logic core with carbon nanotube interconnects could reduce power by 25% and die area by 27%, or increase frequency by 15% and reduce die area by 11%. (iii) A future 22nm 8 GHz 96M gate logic core’s power, die size and optimal multilevel interconnect architecture are predicted. A version of IntSim with a graphical user interface is available for download from www.ece.gatech.edu/research/labs/gsigroup.