A packet scheduler is a primary component of the improved quality of service (QoS) model for today's Internet. Although many fair packet schedulers have been proposed through theoretical consideration, practical high-speed packet schedulers remain elementary. The disparity arises because existent schedulers either lack of necessary QoS guarantee or have an unacceptable cost of computation and storage. In this paper, we propose a simple and efficient packet scheduler called hardware optimized bit reversal permutation (HOBRP) based scheduler. Besides some common merits including low time- and space-complexity, bounded end-to-end delay guarantee and constant fairness index that many well-known schedulers have already owned, our HOBRP still possesses two additional features: One is that the end-to-end delay bound of HOBRP is tunable, which makes itself flexible enough to provide different levels of delay bounds for diverse types of application flows. The other is that all the operations and structures used by HOBRP are very simple and easy to be pipelined and paralleled, which benefits an intuitive high-speed hardware design scheme.

Load-balanced architectures appear to be a promising way to scale Internet to extra high capacity. However, architectures based on mesh topology have a node-degree of N, which prevents these architectures from large node numbers. This consideration motivates us to study the properties of node degree and its impact on the corresponding load-balanced architectures. In this paper we first show the asymptotically minimal node degree for any topology to achieve a constant ideal throughput under uniform traffic pattern when the channel bandwidth is fixed. We further introduce a unidirectional direct interconnection topology, named Plus 2^i (P2i), with this minimal node degree and prove that it has an ideal throughput of no less than twice the channel bandwidth under uniform traffic pattern. Based on the property, we provide the P2i load-balanced (PLB) architecture. Using this architecture, we show that scalability, 100% throughput and packet ordering can be all achieved and the scheduling algorithm is easy to implement. To the best of our knowledge, this is the first load-balanced architecture constructed on multi-hop direct interconnection topologies without packet reordering problem.