Demo Data from VLDB 2026 / reviewers in the wild / expert
Emmanuel Ohayon
dblp:64/8318
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 44% Distributed systems · 44% Storage systems · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Distributed systems › operating system support › interprocess communication
asynchronous message passing |
0.1 | 1 | 2012 | A Model of Parallel Deterministic Real-Time Computation · RTSS 2012 |
Parallel and multicore computing › parallel programming models
message passing |
0.1 | 1 | 2012 | A Model of Parallel Deterministic Real-Time Computation · RTSS 2012 |
Storage systems
error handling |
0.0 | 1 | 2012 | A Model of Parallel Deterministic Real-Time Computation · RTSS 2012 |
Methods — techniques the papers use, named apart from their topics
formal modeling · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Non-Simultaneity as a Design ConstraintabstractWhether one or multiple hardware execution units are activated (i.e. CPU cores), invalid resource sharing, notably due to simultaneous accesses, proves to be problematic as it can yield to unexpected runtime behaviors with negative implications such as security or safety issues. The growing interest for off-the-shelf multi-core architectures in sensitive applications motivates the need for safe resources sharing. If critical sections are a well-known solution from imperative and non-temporized programming models, they fail to provide safety guarantees. By leveraging the time-triggered programming model, this paper aims at enforcing that identified critical windows of computations can never be simultaneously executed. We achieve this result by determining, before an application is compiled, the exact dates during which a task accesses a shared resource, which enables the off-line validation of non-simultaneity constraints. Jean Guyomarc'h, François Guerret, Bilal El Mejjati, Emmanuel Ohayon, Bastien Vincke, Alain Mérigot |
TIME | 4 |
| 2015 | Blind hypervision to protect virtual machine privacy against hypervisor escape vulnerabilitiesabstractHypervision is being widely implemented in an effort to control costs and to simplify management through consolidation of servers. It has been recently unraveled that well over a third of virtualization vulnerabilities reside in the hyper-visor, mostly due to hypervisor escape. The exploitation of these vulnerabilities allows an attacker, among other things, to access and/or modify data of other Virtual Machines (VMs) by escaping from its VM and executing malicious code in the hypervisor. This paper introduces the general idea of blind hypervision, a hardware/software co-design to prevent such attackers to access private elements of other VMs. Blind hypervision limits the rights of the hypervisor regarding memory access, so that a malicious agent executing with hypervisor rights cannot access the data of the VMs. Paul Dubrulle, Renaud Sirdey, Philippe Dore, M. Aichouch, Emmanuel Ohayon |
INDIN | 5 |
| 2012 | A Model of Parallel Deterministic Real-Time ComputationabstractThis paper presents a model of computation based on real-time constraints and asynchronous message passing, and proves a sufficient and necessary condition for this model to be deterministic. The model is then extended with deterministic error handling, meaning that the same error yields the same consequences on the system. We consider two different error occurrence models: at a specific time, or at a specific instruction, and conclude that the "error at a specific time" model is more suitable for practical use. We proceed by presenting a concrete implementation of this model in the PharOS real-time system. Matthieu Lemerre, Emmanuel Ohayon |
RTSS | 2 |