The power consumed when writing to some emerging memory arrays, such as certain varieties of Resistive Random Access Memory (RRAM), is significantly greater than that consumed by many charge-based memories such as SRAM. As a result, when used in applications where instantaneous power consumption is constrained, the number of bit transitions is limited. In this paper, we present modular, low cost, power-efficient differential bus encoders (DBEs) and (related) encoders for error correcting codes. Combining a DBE module and an encoder for a power-efficient single error correcting (PESEC) code ensures low-power operation and reliable data storage, and with a minor modification, a PESEC encoder becomes a PESEC+DED encoder. These encoders make use of systematic, multiple-representation based, error correcting codes. It is shown that when one of our DBEs is used with one of these PESEC encoders, the combined system requires about twenty-five percent fewer bit transitions and ten to twenty percent fewer redundant bits than similar techniques. Moreover, the addition of a PESEC encoder only causes a marginal change in implementation cost relative to that of an encoder for a standard Hamming code. Furthermore, the techniques proposed here do not require huge lookup tables, as do other power-aware techniques. Finally, our PESEC encoders can be used withanybus encoder.

Certain emerging memory technologies such as Resistive RAM (RRAM) require a relatively large amount of energy when changing the value of a bit. When working under strict instantaneous power constraints, it is necessary to limit the maximum number of bit transitions (bit-flips) that can be made when writing a word. To this end, binary, power-efficient, double-error-correcting (PEDEC) codes are introduced. For standard data widths (multiples of eight bits), PEDEC codes offer reductions in both the number of bit transitions and the memory width. PEDEC codes are encoded systematically, and their redundant part is generated by making use of coset codes that are carefully designed so that their coset leaders are easy to generate. For this reason, PEDEC codes do not require the very large lookup tables required by the competing codes and can be concatenated with any bus encoder.

The power consumed when writing to Resistive Random Access Memory (RRAM) is significantly greater than that consumed by many charge-based memories such as SRAM, DRAM and NAND-Flash memories. As a result, when used in applications where instantaneous power consumption is constrained, the number of bits that can be set or reset must not exceed a certain threshold. In this paper, we present a power-efficient, single error correcting (PESEC) code for memory macros, which, when combined with bus encoding, ensures low-power operation and reliable data storage. This systematic, multiple-representation based single-error correcting code provides a relatively high rate, with a marginal increase in implementation cost relative to that of a standard Hamming code, and it can be used with any bus encoder.

Bus encoding is a technique for decreasing the power consumption of a chip by reducing the number of bit transitions during data transmission over a bus or during memory write operations. Designers often concatenate a bus encoder with an error correcting code (ECC) encoder to guarantee the reliable and power-aware transmission of data. This paper introduces a structured technique for hardening bus-encoders to enable single error correction (SEC) while maintaining power awareness. The method is based on expurgating the Hamming code in a specific manner. The resulting power-aware (expurgated), SEC code can serve as an add-on solution, when it is desired to add error correction to an existing bus-encoder.

Often, data stored in memory must be protected from naturally occurring and malicious errors. Methods for constructing codes that are robust with respect to errors injected into the data as well as into the address (in which the data are to be stored) are described. Several ways of extending data-protecting codes to address-and-data protecting codes are presented, and a generalization of the concepts behind CPCs – low cost codes for which no error injected into the data is ever completely masked – is given. A fundamental difference between attacks on the address and data and attacks that only target the data is detailed, and the consequences of this fundamental difference are briefly considered.

Transmission across a bus modelled as a parallel asynchronous communication channel is subject to fault injection attacks which cause glitches - pulses that are added to the transmitted signal at arbitrary times - and delays. We present self-synchronizing coding schemes with no latency at the receiver that do not require any acknowledgment to be sent and that can decode the received signal even when the signal suffers from random delays and distortion by random glitches. We make use of the codes to produce lower bounds on the information capacity of such channels when the number of parallel channels is large.

Transmissions across asynchronous communication channels are subject to delay injection attacks, which can cause an arbitrary number of skews. That is, such attacks can cause an arbitrary number of transmitted signals to arrive after the first signal of the next transmission has arrived. The (common) assumption that despite the delays, all signals from the ith transmission arrive at the decoder before any signal from the (i+2)nd transmission arrives is called a no switch assumption. This paper presents a self-synchronizing, zero-latency, zero-error coding scheme that requires no acknowledge and can decode transmissions distorted by an arbitrary number of skews that obey this no switch assumption. The rate associated with the coding scheme provides a lower bound of 0.6942 for the (zero-error) capacity of such a channel. It is further shown that zero-error channel capacity of the channel is upper bounded by 0.7248. Finally, this paper presents bounds on the (zero-error) capacity of a channel for which the number of transmissions that can mix with one another is large.

Transmission across asynchronous communication channels can be subjected to delay injection attacks. Delay injection attacks cause arbitrary skews - arbitrary numbers of transmitted signals can arrive after the first signal of the next transmission has arrived. The (common) assumption that all signals form the ithtransmission arrive at the decoder before any signal from the (i + 2)thtransmission arrives is called a no switch assumption. This paper presents a self-synchronizing zero-latency coding scheme that requires no acknowledge and can perfectly decode any transmission distorted by an arbitrary skew that obeys the no switch assumption.

This paper presents generalizations of the Karpovsky-Taubin nonlinear code. The generalizations lead to robust and partially robust single error detecting codes and single error correcting codes.