The paper introduces an Autoware autonomous driving software stack powered open-source AV shuttle devel-opment summary and an overview of experiments conducted on it within recent years. The vehicle is built on an OEM electrical vehicle platform, but middle-layer electronics and embedded software are built by the students and researchers team of the Tallinn University of Technology (TalTech) AVs research group. The initial body of the vehicle is designed and manufactured by an Estonian company that contributes significantly to the project. The shuttle has enabled the conduct of many scientific and innovation experiments and contributed to many EU and US projects in very broad aspects related to autonomous mobility. A selection of the most relevant experiments, like advanced overtaking, the language of driving, cybersecurity, mobility as a service (Maas), verification and validation, are briefly covered in this paper. The shuttle is powered by open-source autonomous driving software Autoware and Robot Operating System (ROS), both of which are open-source software. After the end of the project's first stage and the first five vehicles, the project forked to a commercial version owned by Estonian company AuVe Tech and the R&D version owned by TalTech. This paper focuses on the latter, uniquely offering our description and lesson learned in designing our L4 autonomous open-source fully functional research and development vehicle for other research organizations worldwide.

Validation and Verification (V&V) of complex Autonomous Vehicle (AV) systems is currently an unsolved problem. In response, PolyVerif, an open-source AV V&V project, was released with the objective of accelerating research in this important area. PolyVerif provided a full open-source stack consisting of an AV engine, symbolic test generation, simulations at various levels of fidelity, a digital twin creation environment, and a flow from simulation tests to construct physical tests. This demonstration will present a series of “Design for Test” modules focused on the major pieces of an AV stack - Detection, Location Services, Control, and Path Planning. Taken together, these modules build a framework to validate complex AV stacks.

A crisis is a terrible thing to waste. Quotes like this are often heard by experts in the industry and academia but what does this mean to me? How should I change my professional interests? How should I evolve my career? How is EDA going to evolve? The panel represents multiple points of views on these questions. Four experts will review the current job situation in EDA and provide a historical perspective for previous recessions. The panel will further discuss views on new directions for the Electronics market, how EDA should evolve, and options for career development during the slow down of the industry.

Technical computing has unique requirements which are exemplified by factors such as: an extreme focus on run-time performance, a high degree of responsiveness to the customer base, a continued focus on innovation, concurrent support on multiple computing platforms and most importantly, a very limited set of deep subject matter experts who have the skills to build the solution. Exacerbating the above issues is the fact that the field has traditionally seen a great deal of mergers and acquisition activity which leads quickly to an accumulation of disjoint software development systems. This paper describes a detailed case study built within a leading technical computing company which achieved significant success by focusing relentlessly on enhancing the productivity of the individual developer. The work was driven by the author as the general manager of the organization, and measured results of the transformation will be presented in this paper.

In this paper we present our method of formal verification of the transistor implementation of the Bus Interface Unit (BIU) of the Alpha 21264 microprocessor. We compare the logical description compiled from the Register Transfer Level (RTL) against that extracted from the custom-designed transistor-level schematics. BOVE, our BDD-based verification tool, does not require latch-to-latch correspondence, thus allowing the RTL to be more stable during the design process and giving the schematic designers freedom to implement race and timing optimizations. A unique "retiming" comparison algorithm efficiently compares partitions that include multiple pipeline stages, retiming optimizations and precharge logic. BOVE also verifies small finite-state machines that have different state encodings in the RTL and schematic.

Programmable reduced instruction set computers (PRISC) are a new class of computers which can offer a programmable functional unit (PFU) in the context of a RISC datapath. PRISC create application-specific instructions to accelerate the performance for a particular application. Our previous work has demonstrated that peephole optimizations in a compiler can utilize PFU resources to accelerate the performance of general purpose programs. However these compiler optimizations are limited by the structure of the input source code. This work generalizes on our previous work, and demonstrates that the performance of general abstract data types such as short-set vectors, hash tables, and finite state machines is significantly accelerated (250%-500%) by using PFU resources. Thus, a wide variety of end-user applications can be specifically designed to use PFU resources to accelerate performance. Results from applications in the domain of computer-aided design (CAD) are presented to demonstrate the usefulness of our techniques.>

This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as programmable instruction set computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. We concentrate on the microarchitectural design of the simplest form of PRISC-a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language compilation techniques that are needed to successfully build PRISC and, we present performance results from a proof-of-concept study. With the inclusion of a single 32-bit-wide PFU whose hardware cost is less than that of a 1 kilobyte SRAM, our study shows a 22% improvement in processor performance on the SPECint92 benchmarks.

A clock suppression based technique that takes advantage of the higher abstraction level provided by synchronous design techniques to improve logic simulation performance was given by the authors (see Proc. IEEE Int. Conf. on Comput. Aided Des. Integr. Circuit Syst., pp.62-65, 1990). Here, the authors elaborate on those techniques and present extensions that can offer an average performance increase of over 5* and a peak performance increase of over 10* that of a conventional logic simulator. The viability of the approach is shown by presenting results from switch-level simulations of large industrial examples. It is shown that because clock suppression based techniques are CPU-bound, they can take advantage of the recent explosive growth of CPU performance.>

Static timing verifiers need to know at which points data are synchronized with clocks in a circuit. Typically, this happens at latches and in clock qualification gates. However, in a general, full-custom VLSI methodology, the 'latch-equivalents' are far more varied and difficult to detect reliably. The authors define these synchronization points, and present provably robust algorithms to locate them in a very general class of MOS networks, including arbitrary pass gates. The algorithms have been applied to a variety of full-custom CPUs of up to 500 K devices, and have been found to work extremely reliably and quite fast.>

An overwhelming majority of logic designers use synchronous logic design techniques to manage the complexity of their designs and rely on logic simulation techniques for design verification. Yet, logic simulators do not take advantage of the higher abstraction level provided by synchronous logic design techniques to improve their performance. A general technique is presented which takes advantage of the high degree of periodicity common in synchronous logic designs. It is shown that a performance improvement of at least 200% occurs when these techniques are applied within the COSMOS. simulation system to simulate large digital systems.>

A global feedback detection algorithm for VLSI circuits is presented. It can identify all the global feedback loops within reasonable computational time. The overall algorithm is as follows: First, all the strongly connected components (SCC) are found using a modified version of the Tarjan algorithm which can handle circuits with flip-flops and latches. Second, each SCC recursively cuts the loops based on heuristic criteria to reduce computation time and space until all loops inside this SCC are out. The modified Tarjan algorithm for finding SCCs in circuits consisting of functional primitive elements such as flip-flops and latches is described. A recursive loop-cutting algorithm for strongly connected components is presented, and a top-level partitioning scheme to reduce memory requirements and computation time for finding global feedback loops is proposed.>

The authors present ITPG (Interactive Test Pattern Generator), an automatic test pattern generation tool which produces high fault coverage for complex sequential circuits. The tool is more successful than previous attempts at sequential test generation because of the innovative heuristics and high-level sequential primitives used in the system. Old heuristics, such as controllability and observability, have been extended to the sequential world, and a new heuristic, grouping, has been added to accelerate sequential test pattern generation. In addition, the tool allows the designer to influence the test generation process, thus resulting in the 'interactive' nature of the tool. Results from real industrial VLSI circuits show the effectiveness of this tool.>

In this paper, a general methodology for design rule development and the CAD tool which implements this methodology, Statistical Design Rule Developer (STRUDEL), are presented. The focus of the proposed approach is the concept of a statistical design rule, which is defined as a geometric design rule with an associated probability of failure. Global lateral variations obtained from FABRICS, and local spot defects obtained from measurements are taken into account when calculating the probability of failure. A failure model which accounts for catastrophic faults has been enhanced to include some parametric faults. STRUDEL can be used as a guide to generate layout design rules and may be extended to a wide range of applications including coarse yield estimation during design rules check.