This letter proposes an algorithm that selects a small number of test patterns for small delay defects from a large N-detect test set. This algorithm uses static upper and lower bound analysis to quickly estimate the sensitized path length so that the central processing unit (CPU) time can be reduced. By ignoring easy faults, only a partial fault dictionary, instead of a complete fault dictionary, is built for test pattern selection. Experimental results on large International Test Conference benchmark circuits show that, with very similar quality, the selected test set is 46% smaller and the CPU time is 42% faster than that of timing-aware automated test pattern generation (ATPG). With the proposed selection algorithm, small delay defect test sets are no longer very expensive to apply.

We present a Linear Feedback Shift Register (LFSR) like architecture, because the LFSR can bring a lot of data by using a few bits. We calculate the ATE data by Gauss-Elimination and put the ATE data to our decompression architecture to generate a lot of patterns. And one ATE data will run several times in the architecture. If some faults cannot be detected, we will generate the patterns which are brought by fault simulation. If still a few faults cannot be detected, the faults will be caught by directly modify the bits of ATE data. The less ATE data we use, the less cycles we need. Because the reason, we can get high speed testing. And the less data, the low-cost environment we need. The cycle we can save is up to 61.60x. And the average rate of compression can get 19.33x.

Generally speaking, the dependency data compression is very useful for Intellectual Property (IP) cores and SoC. We consider the shift-in power and compression ratio in low-cost ATE environment. We propose new compression architecture with fixed length for running ones. We suppose that the ATE has not repeated function and synchronization signal. In the results, when the complexity of VLSI circuit is growing up, the number of input pins for testing is very low. The average compression ratio of our method is 63% for MinTest on ISCAS'89 benchmarks. The average of peak/WTC shift-in turns to 3×/6.6×, after comparing Selective Scan Slice (SSS) and our method. The average of hardware overhead is 6%.

ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents Adjacent Backtracing filling (AB-fillingl) which both adjacent and backtracing filling algorithms are used, is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT. After our approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of don't care value (x) bits as in test compression, and it is a low capture power and considering the shift power test pattern. Experimental results for ISCAS'89 benchmark circuits show that the proposed scheme outperforms previous method in capture power.

A scheme that ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents an X-filling approach called Adjacent Backtracing fill (AB-fill). After AB-fill approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of don’t care bits (x) as in test compression, and it is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT.

This paper presents a test slice difference (TSD) technique to improve test data compression. It is an efficient method and only needs one scan cell. Consequently, hardware overhead is much lower than cyclical scan chains (CSR). As the complexity of VLSI continues to grow, excessive power supply noise has become seriously. We propose a new compression scheme which smooth down the switching activity and reduce the test data volume simultaneously.

In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing (Wang and Chakrabarty, 2008) and our method. The average of improvement/ hardware is 16%/6%.

We present efficient method for reducing test application time by broadcasting test configuration. We compare our method based on single, multiple, 1-1 in-order mapping, even distribution, nearest signal probability matching, and in-order pseudo-exhaustive method. The results of our experiments indicate that our method reducing the test pattern number and the test application time by running the ATPG tool provided by SIS.

In this paper, we present an efficient method for reducing the total length of the scan paths. The method appropriately assigns scan flip-flops into scan chains after these flip-flops being placed. We compare our proposed method with previous work based on pre-placement (PP), greedy (GR), and stable marriage (SM) assignment, and show that our method is superior to the previous approaches. We also perform our method on some of the ISCAS 89 benchmarks. The obtained results of our experiments indicate that our algorithm improves the scan chain lengths by 79%-96% and the CPU time almost increases linearly.

Because of its ability to detect all nonredundant combinational faults, exhaustive testing, which applies all possible input combinations to a circuit, is an attractive test method. However, the test application time for exhaustive testing can be very large. To reduce the test time, pseudoexhaustive testing inserts some bypass storage cells (bscs) so that the dependency of each node is within some predetermined value. Though bsc insertion can reduce the test time, it may increase circuit delay, In this paper, our objective is to reduce the delay penalty of bsc insertion for pseudoexhaustive testing. We first propose a tight delay lower bound algorithm, which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, ne can propose a bsc insertion heuristic that tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.

The object of this paper is to reduce the delay penalty of bypass storage cell (bsc) insertion for pseudo-exhaustive testing. We first propose a tight delay lower bound algorithm which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, we can propose a bsc insertion heuristic which tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.

A factored form of a Boolean function is a common representation to express the complexity of a Boolean function in multi-level logic. However, a factored form which inhibits the appearance of the inversion operation is still a restricted way of representing a multi-level circuit. In this paper, we present a novel representation of a Boolean function, called the invert factored form representation. This representation mainly takes advantage of the inversion of whole or part of a Boolean function so that fewer literals and better multi-level circuit implementation can be obtained. Based on this novel presentation, our algorithm attempts to find a minimal expression. Experimental results also show the literal counts based on the novel representation are smaller than those on the traditional factored form representation.

This paper presents a new test architecture, called Tree-LFSR/SR, to more effectively generate pseudo-exhaustive test patterns for combinational VLSI circuits. Instead of using a single scan chain, the proposed test architecture routes a scan tree driven by the LFSR to generate all possible input patterns for each output cone. The new test architecture is able to take advantages of both signal sharing and signal reuse. The benefits are: (1) the hardware overhead can be greatly reduced by saving routing area and XOR circuits, and (2) the difficulty of test architecture synthesis can be eased by accelerating the searching process of appropriate residues. The Tree-LFSR/SR configuration is then extended, if necessary, by adding XOR networks to deal with more complex input-output relations. An efficient method to directly synthesize the XOR network is also included. Experimental results obtained by simulating combinational benchmark circuits are very encouraging.