Recently, AI acceleration is critical for hardware systems from mobile/edge devices to high-performance data servers. For on-device AI, there have been many studies on hardware numerical precision reduction for low hardware complexity considering limited hardware resources of mobile/edge devices [1–2]. However, if taken too far, aggressive quantization with low precision can degrade model accuracy which is the fundamental measure of deep learning quality. With the layer-wise mixed-precision networks where the different precision scheme is applied to each layer, we can reduce off-chip memory bandwidth requirements as well as hardware complexity while retaining model accuracy [3]. However, it takes a long time to determine the optimal precision scheme for each layer due to the repetitive trainings with the different precision configurations. Also, if only the accuracy of the target neural network is considered in the process of the mixed-precision determination, it is difficult to sufficiently reduce the computational complexity, which is the most important in mobile/edge devices [4].

This paper presents a stage-level clock-gating scheme for clock power improvement. The proposed technique efficiently implements the concept of transparent pipeline which improves clocking power by dynamically making pipeline registers transparent. We developed new control scheme for transparent pipeline which can be applied to any number of pipeline stages. A low-overhead flip-flop with transparent mode is also proposed to reduce implementation overhead. The proposed clock-gating control logic is extended to pipeline collapsing which allows energy/performance trade-off through dynamic frequency scaling. Simulation results on IBM 90 nm technology show that the proposed approach has less overhead (~25%) than the previous transparent pipeline scheme and improves up to 40% of clocking power in 64-bit 7-stage pipeline over traditional stage-level clock-gating technique.

This paper presents a dynamic bit-width adaptation scheme for applications using discrete cosine transform (DCT). The technique can efficiently trade off image quality and computation energy. Based on sensitivity differences of 64 DCT coefficients, separate operand bit-widths are used for different frequency components to reduce computation energy. To select the appropriate operand bit-widths that achieve significant reduction of power consumption with minimum image quality degradation, we also propose a bit-width selection algorithm. The proposed variable bit precision DCT algorithm can be efficiently implemented using carry save adder trees. The reconfigurable DCT architecture can achieve power savings ranging from 36% to 75% compared to normal operation at the expense of minor image quality degradation.

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and ldquooutput quality.rdquo In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the ldquoless important computationsrdquo are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings.

In this paper, we present a novel finite-impulse response (FIR) filter synthesis technique that allows for aggressive voltage scaling by exploiting the fact that all filter coefficients are not equally important to obtain a ldquoreasonably accuraterdquo filter response. Our technique implements a level-constrained common-subexpression-elimination algorithm, where we can constrain the number of adder levels (ALs) required to compute each of the coefficient outputs. By specifying a tighter constraint (in terms of the number of adders in the critical path) on the important coefficients, we ensure that the later computational steps compute only the less important coefficient outputs. In case of delay variations due to voltage scaling and/or process variations, only the less important outputs are affected, resulting in graceful degradation of filter quality. The proposed architecture, therefore, lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under extreme process variation and supply voltage scaling (0.8 V), filters implemented in the predictive technology model (PTM) 70 nm technology show an average power savings of 25%-30% with minor degradation in filter response in terms of normalized passband/stopband ripple (0.02 at a scaled voltage of 0.8 V compared with 0.005 at a nominal supply).

In this paper, we propose O2C, a novel non-speculative adaptive thermal management technique that reduces the temperature during die-overheating using supply voltage scaling, while maintaining the rated clock frequency. This is accomplished by (a) scaling down the supply voltage, (b) isolating and predicting the set of critical paths, (c) ensuring (by design) that they are activated rarely, and (d) getting around occasional delay failures (at reduced voltage during die-overheating) in these paths by two-cycle operations (assuming all standard operations are single-cycle). Two-cycle operation is achieved by stalling the pipeline for extra clock cycles whenever the set of critical paths are activated. The rare two-cycle operation results in a small decrease in IPC (instructions per cycle). Since called maintains the rated clock frequency and does not require pipeline stalling during supply voltage ramp-up/ramp-down, it achieves high throughput in a thermally constrained environment. We applied called to the integer execution units of an in-order superscalar pipeline. Standard full-chip Dynamic Voltage-Frequency Scaling (DVFS) is very effective in bringing down the temperature, however; it is associated with large throughput loss due to pipeline stalling and slow operating frequency during thermal management. We integrated O2C with standard (called O2Cα) to demonstrate that it can act as a first step before full-scale thermal management is required. Our simulations indeed reveal that called O2Cα policy can avoid the requirement of full-scale DVFS during execution of programs.

In this paper, a profit-aware design metric is proposed to consider the overall merit of a design in terms of power and performance. A statistical design methodology is then developed to improve the economic merit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve economic gain of a design over its initial yield-optimized design. Finally, we present an integrated design methodology for simultaneous sizing and bin boundary determination to enhance profit under an area constraint. Experiments on a set of ISCAS'85 benchmarks show in average 19% improvement in profit for simultaneous sizing and bin boundary determination, considering both leakage power dissipation and delay bounds compared to a design initially optimized for 90% yield at iso-area in 70-nm bulk CMOS technology.

With technology scaling, devices are increasingly prone to process variations. These variations cause a large spread in leakage power, since it is extremely sensitive to process variations, which in turn results in larger temperature variations across different dies. In this paper, we investigate the temperature variations in FinFET circuits considering variations in following parameters (i) channel length and (ii) body thickness. We estimate temperature variation under process fluctuation by Monte Carlo simulation with thermal models to solve temperature and leakage power self-consistently. The results show that high activity circuits exhibit larger temperature variations since increased temperature increments leakage power and vice versa. It is also shown that under moderate process variation (3sigma=10% for channel length and body thickness) and a nominal primary input activity of 0.4, thermal runaway can occur in more than 15% of chips in 28 nm FinFET technology, severely degrading manufacturing yield.

In this paper, we present a novel FIR filter synthesis technique that allows aggressive voltage scaling by exploiting the fact that all filter coefficients are not equally important to obtain a "reasonably accurate" filter response. Our technique implements a Level Constrained Common Subexpression Elimination (LCCSE) algorithm, where we can constrain the number of adder levels required to compute each of the coefficient outputs. By specifying a tighter constraint (in terms of number of adders in the critical path) on the important coefficients, we ensure that the later computational steps compute only the less important coefficient outputs. In case of delay variations due to voltage scaling and/or process variations, only the less important outputs are affected, resulting in graceful degradation of filter quality. The proposed architecture, therefore, lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under extreme process variation and supply voltage scaling (0.8V), filters implemented in BPTM 70 nm technology show an average power savings of 25-30% with minor degradation in filter response.

In this paper, we propose a methodology to solve leakage power self-consistently with temperature to predict thermal runaway. We target 28-nm-technology-node FinFET-based circuits as they are more prone to thermal runaway because of self-heating and less efficient heat dissipation compared to bulk metal-oxide-semiconductor field-effect transistors. We have generated thermal models for logic cells-inverter, NAND, and NOR-to self-consistently determine the temperature map of a circuit block. Our cell-level thermal models account for lateral heat flow (contribution of neighboring cells) along with vertical heat dissipation to the heat sink. We predict positive feedback between subthreshold leakage and temperature for all the cells in a given floor plan. Our proposed condition for thermal runaway shows the design tradeoff between the primary input (PI) activity of a circuit block, subthreshold leakage at the room temperature, and thermal resistance of the package. We show that, in FinFET circuits, thermal runaway can occur at the International Technology Roadmap for Semiconductors-specified subthreshold leakage (of 150 for high performance) for a nominal PI activity of 0.5 and typical package thermal resistance. In addition, we show that the maximum temperature rise in an integrated circuit is limited by package limitations.

With technology scaling, elevated temperatures caused by increased power density create a critical bottleneck modulating the circuit operation. With the advent of FinFET technologies, cooling of a circuit is becoming a bigger challenge because of the thick buried oxide inhibiting the heat flow to the heat sink and confined ultra-thin channel increasing the thermal resistivity. In this work, we propose compact thermal models to predict the temperature rise in FinFET structures. We develop cell-level compact thermal models for standard INV, NAND and NOR gates accounting for the heat transfer across the six faces of a cell. Temperature maps of benchmark circuits exhibit close correspondence with dynamic power maps because of confined regions of heat generation separated by low thermal conductivity material. It is illustrated that temperature-aware timing analysis is imperative, because of high inter-cell temperature gradient. Accurate prediction of temperature in the early phase of design cycle gives valuable estimation of power/performance/reliability of a circuit block and guides in the design of more robust circuits.

Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-aware yield model, based on which we present a statistical design methodology to improve profit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve the profitability of design over an initial yield-optimized design. We also propose an algorithm to determine optimal bin boundaries for maximizing profit with frequency binning. Finally, we present an integrated design methodology for simultaneous sizing and bin placement to enhance profit under an area constraint. Experiments on a set of ISCAS85 benchmarks show up to 26% (36%) improvement in profit for fixed bin (for simultaneous sizing and bin placement) with three frequency bins considering both leakage and delay bounds compared to a design optimized for 90% yield at iso-area.

We present a dynamic bit-width adaptation scheme in DCT applications for efficient trade-off between image quality and computation energy. Based on sensitivity differences of 64 DCT coefficients, various operand bit-widths are used for different frequency components to reduce computation energy in DCT operation. Numerical results show that our DCT architecture can achieve power savings ranging from 36% to 75% compared to normal operation.

In this work we propose a methodology to self-consistently solve leakage power with temperature to predict thermal runaway. We target 28n m FinFET based circuits as they are more prone to thermal runaway compared to bulk-MOSFETs. We generate thermal models for logic cells to self-consistently determine the temperature map of a circuit block. Our proposed condition for thermal runaway shows the design trade off between the primary input (PI) activity of a circuit block, sub-threshold leakage at the room temperature and the thermal resistance of the package. We show that in FinFET circuits, thermal runaway can occur at the ITRS specified sub-threshold leakage (150nA/μm, highperformance) for a nominal PI activity of 0.5 and typical package thermal resistance.