In the next years, new hash function candidates will replace the old MD5 and SHA-1 standards and the current SHA-2 family. The hash algorithms RadioGatun and irRUPT are potential successors based on a stream structure, which allows the achievement of high throughputs (particularly with long input messages) with minimal area occupation. In this paper, several hardware architectures of the two above mentioned hash algorithms have been investigated. The implementation on ASIC of RadioGatun with a word length of 64 bits shows a complexity of 46 k gate equivalents (GE) and reaches 5.7 Gbps throughput with a 3.64-bit input message. The same design approaches 120 Gbps on ASIC with long input messages (63.4 Gbps on a Virtex-4 FPGA with 2.9 kSlices). On the other hand, the irRUPT core turns out to be the most compact circuit (only 5.8 kGE on ASIC, and 370 Slices on FPGA) achieving 2.4 Gbps (with long input messages) on ASIC, and 1.1 Gbps on FPGA.

A public competition organized by the NIST recently started, with the aim of identifying a new standard for cryptographic hashing (SHA-3). Besides a high security level, candidate algorithms should show good performance on various platforms. While an average performance on high-end processors is generally not critical, implementability and flexibility in hardware is crucial, because the new standard will be implemented in a variety of lightweight devices. This paper investigates VLSI architectures of the SHA-3 candidates MD6 and irRUPT. The fastest circuit is the 16timesparallel MD6 core, reaching 16.3 Gbps at a complexity of 69.8 k gate equivalents (GE) on ASIC and 8.4 Gbps using 4465 Slices on FPGA. However, large memory requirements preclude the application of MD6 to resource-constrained systems. The most flexible and efficient circuit turns out to be our 2-irRUPT64times2-256/8 core, which achieves a throughput of 5.0 Gbps at 12.7 kGE on ASIC and 1.7 Gbps using 613 Slices on FPGA.

Eleven latch circuits for ultra-low-power applications with resonant clocking are compared in terms of energy dissipation (the main focus of this work), propagation delay, set-up, and hold time in a wide range of operating frequencies and supply voltages. Transistor-level simulations in a 0.18 µm process point out that the ratioless circuit Cut Cross-over current latch (CC-Latch) saves up to 15% energy towards the second best competitor in low- to mid-frequency applications. The improved efficiency is due to the suppression of the excess of cross-over current, by switching of the pull-up or the pull-down network alternatively in the forward inverter of the latch.

This paper presents the rst ASIC implementation of the transform, lighting and setup stages of the elliptical weighted average (EWA) surface splatting algorithm, a high quality method for anti-aliased rendering of point sampled objects in computer graphics. The algorithm has been integrated on a small core size of 8.15 mm2in a 180 nm process using massive resource sharing. It achieves the high throughput of 2.94 million points per second at the operating frequency of 147 MHz, with a power dissipation of 300mW.

Various 16-bit multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 mu W/MHz versus 9.6 mu W/MHz for 0.18mum CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 muW/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency further (4.7 muW/MHz), beyond recently published low-power architectures. The innovation consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number ofVdd-to-ground paths also contributes to a significant decrease of static consumption.

This paper analyzes the power-area trade-off of functionally equivalent architectural implementations of a speech enhancement algorithm for hearing aids. Gate-level simulations and measurements show that an optimum degree of resource sharing (0.60 mW in a 0.25 /spl mu/m CMOS process) is more energy-efficient than both the fully time-multiplexed (1.42 mW) and the isomorphic architecture (1.54 mW), without overly large area overhead (0.77 mm/sup 2/ against 0.43 mm/sup 2/ and 4.31 mm/sup 2/, respectively).

Resonant clocking holds the promise of trading speed for energy in CMOS circuits that can afford to operate at low frequency, like hearing aids. An experimental chip with 110k transistors and more than 2500 latches, has been designed, fabricated and tested. The measured energy con sumption of the design at 0.8 V is 62μW/MHz, about 7.5% less than the conventional single-edge-triggered benchmark. Closer analysis reveals that much of the energy savings brought about by resonant clocking at low supply voltages are lost when a CMOS circuit is operated at higher voltages. This is because of the crossover currents that persist for much of a clock period when a circuit is driven from sine-type clock waveform.

Glitches are responsible for a significant proportion of overall power dissipation in digital signal processing circuits. Activity-reduction techniques that involve an optimized clocking strategy have been applied to a front-end block in a DSP adaptive directional microphone for hearing aids. Functionally equivalent implementations, differing only in their clocking scheme, have been integrated on silicon in a 0.25 mum CMOS technology. Measurements and post-layout simulations confirm a 42% reduction over single-edge-triggered clocking with clock gating. An overall power dissipation of 20 muW (@ 1.4 V, 374 kHz) has been measured. This achievement has been made possible by combining two novel techniques: a multi-stage clock gating, and a symmetric two-phase level-sensitive clocking with glitch-aware re-distribution of data-path registers