Ultrasonic signal acquisition platforms generate considerable amounts of data to be stored and processed, especially when multichannel scanning or beamforming is employed. Reducing the mass storage and allowing high-speed data transmissions necessitate the compression of ultrasonic data into a representation with fewer bits. High compression accuracy is crucial in many applications, such as ultrasonic medical imaging and nondestructive testing (NDT). In this study, we present learning models for massive ultrasonic data compression on the order of megabytes. A common and highly efficient compression method for ultrasonic data is signal decomposition and subband elimination using wavelet packet transformation (WPT). We designed an algorithm for finding the wavelet kernel that provides maximum energy compaction and the optimal subband decomposition tree structure for a given ultrasonic signal. Furthermore, the WPT convolutional autoencoder (WPTCAE) compression algorithm is proposed based on the WPT compression tree structure and the use of machine learning for estimating the optimal kernel. To further improve the compression accuracy, an autoencoder (AE) is incorporated into the WPTCAE model to build a hybrid model. The performance of the WPTCAE compression model is examined and benchmarked against other compression algorithms using ultrasonic radio frequency (RF) datasets acquired in NDT and medical imaging applications. The experimental results clearly show that the WPTCAE compression model provides improved compression ratios while maintaining high signal fidelity. The proposed learning models can achieve a compression accuracy of 98% by using only 6% of the original data.

This paper presents two computer architecture mechanisms that can be employed together to allow programs to be written where their individual instructions can (1) be executed in parallel in separate processors and (2) be arbitrarily assigned to be executed by any processor in a connected fabric of processors. This is an emerging parallel execution technique for future high performance and embedded computers. Changing the placement of a program's instructions in a processing fabric is equivalent to rearranging the computer architecture around the program itself. Reasons to change the computer architecture around the software are to improve overall execution speed and to perform load balancing. The two computer architecture mechanisms are (1) a custom dataflow instruction set and (2) a processor block called an operation cell. The most important feature of the instruction set is the high level of operational independence of the instructions (i.e. no shared memory/registers between instructions). The operation cell is a processor construct that stores an instruction and manages the execution life of that instruction. An operation cell either executes the instruction itself or forwards the execution to another operation cell in a different processor.

A dataflow processor is presented that is to be used as the basis of a tiled polymorphic computing architecture. The key contribution is a new scheme that allows a program's instructions to be migrated before and during runtime in a fine-grained manner across the collection of processors. The primary reason to perform this migration is to execute programs faster. Other reasons to perform instruction migration are to prioritize computational resources and to achieve thermal balancing. The act of performing instruction migration across of a collection of processors is logically equivalent to rearranging the computer architecture under the program (i.e., polymorphic computing). Additionally, a new dataflow instruction set which enables the migration is presented. This instruction set is built upon the concept of a single RISC-like dataflow instruction that can atomically execute, make decisions, and independently route results. Furthermore, the novel concept of an operation cell is presented. An operation cell holds a single instruction and its data. It also contains logic to independently determine when an instruction is executed and when to forward data to other operation cells in the collection of processors. In addition, the internal architecture of this processor is presented. This includes the arithmetic logic unit (ALU) that is used to execute the instructions and a series of buses that allow data movement to occur in parallel to instruction execution. Finally, an inter-processor migration strategy is defined.

We study the convergence properties of distributed network selection in HetNets with priority-based service. Clients in such networks have different priority weights (e.g., QoS requirements, scheduling policies, etc.) for different access networks and act selfishly to maximize their own throughput. We formulate the problem as a non-cooperative game, and study its convergence for two models: (i) A purely client-centric model where each client uses its own preference to select a network, and (ii) a hybrid client-network model that uses a combination of client and network preferences to arrive at pairings. Our results reveal that: (a) Pure client-centric network selection with generic weights can result in infinite oscillations for any improvement path (i.e., shows strongly cyclic behavior). However, we show that under several classes of practical priority weights (e.g., weights that achieve different notions of fairness) or under additional client-side policies, convergence can be guaranteed; (b) We study convergence time under client-centric model and provide tight polynomial and linear bounds; (c) We show that applying a minimal amount of network control in the hybrid model, guarantees convergence for clients with generic weights. We also introduce a controllable knob that network controller can employ to balance between convergence time and its network-wide objective with predictable tradeoff.

Ultrasonic systems are widely used in imaging applications for non‐destructive evaluation, quality assurance and medical diagnosis. These applications require large volumes of data to be processed, stored and/or transmitted in real‐time. Therefore it is essential to compress the acquired ultrasonic radio frequency (RF) signal without inadvertently degrading desirable signal features. In this paper, two algorithms for ultrasonic signal compression are analysed based on: sub‐band elimination using discrete wavelet transform; and decimation/interpolation using time‐shift property of Fourier transform. Both algorithms offer high signal reconstruction quality with a peak signal‐to‐noise ratio (PSNR) between 36 to 39 dB for minimum 80% compression. The computational loads and signal reconstruction quality are examined in order to determine the best compression method in terms of the choice of DWT kernel, sub‐band decomposition architecture and computational efficiency. Furthermore, for compressing a large amount of volumetric information, three‐dimensional (3D) compression algorithms are designed by utilising the temporal and spatial correlation properties of the ultrasonic RF signals. The performance analysis indicates that the 3D compression algorithm presented in this paper offers an overall 3D compression ratio of 95% with a minimum PSNR of 27 dB.

Sparse signal decomposition techniques used for ultrasonic signal analysis are mainly based on the matching pursuit (MP) method using generic time-frequency dictionaries or more specific dictionaries designed for ultrasound measurements. These dictionary-based MP (DBMP) methods often perform inadequately in extracting meaningful echo components because of the rigid structure of pre-defined dictionaries. More recently emerged model-based signal decomposition methods decompose an ultrasonic signal in terms of parametric model echoes using successive echo partitioning, parameter estimation and echo subtraction. Although these techniques offer more flexibility in signal decomposition, they still use correlation in matching parametric model echoes to partitioned signal components. This study presents a model-based estimation pursuit (MBEP) method that utilises statistical estimation principles in echo matching, as a result provides a greater flexibility and control in signal decomposition. In particular MBEP algorithm utilises maximum a posteriori estimation and incorporates prior knowledge into signal decomposition. Unlike DBMP methods, MBEP obtains physically meaningful decompositions that have direct interpretations for ultrasonic testing. The superior performance of MBEP has been demonstrated using simulated and experimental ultrasonic signals.

In this paper, a new pipelined, reduced memory CORDIC-based architecture is presented for any radix size FFT. A multi-bank memory structure and the corresponding addressing scheme are used to realize the parallel and in-place data accesses. The proposed memory-reduced CORDIC algorithm eliminates the need for storing twiddle factors and angles, resulting in significant area savings with no negative impact on performance. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic.

In various signal processing applications, decomposition and analysis of non-stationary signals is a challenging problem. In this work, we present a computationally efficient method, fast chirplet signal decomposition (FCSD) algorithm, for decomposing highly convoluted signals into a linear expansion of chirplets, and successively estimates the chirplet parameters. These parameters are capable of representing a broad range of echo shapes, including the broad-band, narrow-band, symmetric, skewed, nondispersive or dispersive, and have significant physical interpretations for radar, sonar, and ultrasonic imaging applications. For the real-time implementation of chirplet signal decomposition algorithm, an FPGA-based hardware/software co-design is developed on Xilinx Virtex II Pro FPGA platform. In this study, based on the balance among the system constraints, cost, and the efficiency of estimations, the performance of different algorithm implementation schemes have been explored. The developed system successfully exhibits the robustness in the chirplet signal decomposition of experimental signals. This type of study addresses a broad range of applications including velocity measurement, target detection, deconvolution, object classification, data compression, and pattern recognition.

This paper studies an adder technique that performs three input addition utilizing parallel prefix adders. The adder architectures are called three-input flagged prefix adders (TIFPA) due to the utilization of a new set of intermediate outputs called flag bits to obtain the desired result. One of the advantages of this technique is the elimination of dedicated adder units to perform three-input addition. This adder can find its use in applications such as multiplication or multi-media units. This paper examines the effect on the performance of the adder when the operand size is expanded from 16 bits to 32 and 64 bits. Furthermore, a logical effort analysis has also been performed on the TIFPA to confirm the simulation and analytical results. The performance of this adder design has been compared to that of carry save adders (CSA) to understand the performance gain of the proposed technique. The comparison has been made with respect to the simulation results and also on the basis of logical effort.

This letter presents a fast chirplet transform (FCT) algorithm, a computationally efficient method, for decomposing highly convoluted signals into a linear expansion of chirplets. The FCT algorithm successively estimates the chirplet parameters in order to represent a broad range of chirplet shapes, including the broadband, narrowband, symmetric, skewed, nondispersive, or dispersive. These parameters have significant physical interpretations for radar, sonar, seismic, and ultrasonic applications. For the real-time application and embedded implementation of the FCT algorithm, an FPGA-based hardware/software co-design is developed on Xilinx Virtex-II Pro FPGA development platform. Based on the balance among the system constraints, cost, and the efficiency of estimations, the performance of different algorithm implementation schemes have been explored. The developed system-on-chip successfully exhibits robustness in the chirplet transform of experimental signals. The FCT algorithm addresses a broad range of applications including velocity measurement, target detection, deconvolution, object classification, data compression, and pattern recognition.

Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite Field Extensions Unit with MicroBlaze processor in a Xilinx Virtex2Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2163 ) multiplier, a speed-up factor of 1530X has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.

For multi-operand addition, several techniques, such as carry-save adders, Wallace, and Dadda structures based on counters and compressors have been proposed. This paper proposes a technique to accomplish three-operand addition utilizing regular adder structures such as parallel-prefix adders. One of the advantages of this technique is the elimination of dedicated adder units to perform three-input addition. Conventional prefix adders are modified to generate intermediate outputs called flag bits to allow the addition of a third arbitrary number, thereby accomplishing multi-operand addition. This adder can find its use in applications such as multiplication or multi-media units. An evaluation has been performed for 16-bit three-input flagged prefix adder architectures (TIFPA) in terms of area, delay and power. The performance of this adder design has been compared to that of carry save adders to understand the performance gain of the proposed technique.

The decimal arithmetic has been receiving an increased attention because of the growth of financial and scientific applications requiring high precision and increased computing power. This paper presents an efficient architecture for multi-digit decimal addition based on carry-free signed-digit numbers. In this study, the decimal adder architecture has been designed and synthesized using the TSMC 0.18μ technology. The synthesis results were compared to the existing decimal adders with respect to design area, delay and power consumption. These results show that proposed adder architecture improves the area-delay factor by 3 for a 32 digit adder.

We present a reconfigurable ultrasonic processor which can simultaneously employ two different ultrasonic imaging applications: ultrasonic target detection and signal compression. The underlying hardware design makes use of the fact that both applications share the same algorithm fundamentals. A unified architecture implements signal decomposition and reconstruction with forward and inverse DCT and DWT. After the forward transform step, a thresholding operation is applied to discriminate either frequency bands for target detection or coefficient amplitudes for data compression. The flexibility and the modular design make this reconfigurable architecture an effective and practical solution for real-time ultrasonic imaging applications.

By combining the conventional order-statistic filtering concept with the split-spectrum processing (SSP) technique, a method called frequency-diverse statistic filtering is obtained. Three types of frequency-diverse statistic filters, namely, weighted mean, median, and absolute-minimization, are examined. It is shown that if the target and the clutter spectra are known individually, the Weiner filter can be realized by frequency-diverse statistic filtering using a linear operation (i.e. weighted mean). However, if only the input signal is known, the frequency-diverse statistic filter with a nonlinear order-statistic operation (i.e. median or absolute-minimization) can be used, resulting in SNR (signal/noise ratio) enhancement. Both computer simulation and experimental data have been used to evaluate the performance of the filters and verify the theoretical analyses.>