Silicon-based CMOS technologies are fast approaching their ultimate limits. By approaching these limits, fabrication yield, reliability, and power densities, worsen steadily making further nanometric scaling increasingly difficult. These problems would become showstoppers in ultimate-CMOS and post-CMOS technologies, unless efficient fault-mitigation and low-power approaches are developed to maintain acceptable levels of yield, reliability, and power densities. This paper describes the GRAAL architecture, which improves significantly the fault detection efficiency, cost, and timing constraints of the double-sampling approach, providing this way an efficient scheme for solving the issues induced by aggressive technology scaling in the era of ultimate-CMOS and post-CMOS technologies.

Aggressive technology scaling has dramatic impact on process, voltage and temperature (PVT) variations; circuit aging and wearout; clock skews; sensitivity to EMI (e.g. crosstalk and ground bounce), sensitivity to radiation-induced SEUs SETs; as well as power dissipation and thermal constraints. The resulting high defect rates and design complexity, adversely affect fabrication yield and reliability.

A fault tolerant routing algorithm for 2D Mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime failures that result in message corruption, the routing algorithm is enhanced with packet retransmission and a new packet recovery scheme. Simulation results, under various case studies, with different permanent, transient and intermittent link faults, and under different failure rates demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies.

A memetic algorithm for computing the capacitance coupling in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is based on an approximate extended version of the method of images, is general and applicable to an arbitrary geometry and configuration of conductors. Simulation results are presented for several practical case studies where our method is compared with a commercial tool employing the Finite Element Method (FEM). The capacitance value computed by the proposed method is shown to be in close agreement with the value obtained by the commercial tool with the average difference kept below 3%, thus revealing the efficiency of the proposed scheme.

A method for computing mutual inductance between interconnects of rectangular geometry in Very Large Scale Integrated (VLSI) circuits is presented in this work. The method is general and does not rely on any fitting techniques. It is shown to be computational efficient and numerical stable even for very long interconnects. Simulation results with other methods from literature are presented. The mutual inductance value computed by the proposed method is shown to be in close agreement to the value obtained by the industry standard tool-FastHenry with the average error falling below 5%.

Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to come. Through-silicon-vias (TSV) processes offer a step towards 3D integration. In this work, the aspects of inductors in the TSV technologies are studied. Various TSV inductor topologies are examined both theoretically and by means of numerical simulations. As results show, true 3D vertical inductor designs offer improvements in inductance and quality factor over the planar ones.

In this paper a test method based on the wavelet transformation of the measured signal, be it supply current (IPS) or output voltage (VOUT) waveform, is presented. In the wavelet analysis, a test metric named discrimination factor is introduced utilizing information from initial two decomposition levels of the measured signal. The tolerance limit for the good circuit is set by statistical processing data obtained from the fault-free circuit. Experimental comparative results between the proposed method, a test method based on the RMS value of the measured signal, a test method utilizing the harmonic magnitude components of the measured signal spectrum and a method based on the wavelet transformation of the measured signal are presented showing the effectiveness of the proposed testing scheme.

In this paper a test method based on the wavelet transformation of the measured supply current (IPS) and load current (IL) waveforms is presented. In the wavelet analysis, the test metrics used are utilizing the initial three decomposition levels of the measured signal. Experimental comparative results between the proposed method, a test method based on the RMS value of IPS, a test method utilizing the harmonic magnitude components of the IPSspectrum and a method based on the wavelet transformation of the IPSare presented showing the effectiveness of the proposed testing scheme.

The test sequence compaction problem is modelled here, as a set covering problem. This formulation enables the straightforward application of set covering methods for compaction. Because of the complexity inherent in the first model, a second more efficient, formulation is proposed where the test sequences are modelled as matrix columns with variable costs (number of vectors). Further, matrix reduction rules appropriate to the new formulation, which do not affect the optimality of the solution, are introduced. Finally, the reduced problem is minimized with a branch & bound algorithm. Experiments on a large number of test sets show significant reductions to the original problem by simply using the presented reduction rules. Experimental results comparing our method with others form the literature and also with the absolute minima of the examples, computed separately with the MINCOV algorithm, support the potential of the proposed approach.

The problem of compacting a set of test sequences for sequential circuits is modeled here with the help of a covering matrix, where the test sequences are modeled as columns with variable cost to reflect the cost (number of vectors) of covering selected subsets of circuit faults. From this formulation, reduction rules are extracted, particular to this type of problem which, iteratively applied, result in a significant reduction of the size of the initial compaction problem. A characteristic of the reduction rules is that their application will not compromise the optimum solution of the problem. The remaining reduced problem is then solved by a combination of a heuristic and an exact branch and bound algorithm. Experimental results using the above reduction rules show that the sizes of the given sets of test sequences are often significantly reduced and many times these rules directly produce the absolute minimum of the solution. The final results, compared with others from the literature and also with the absolute minima of the examples, computed separately, support the potential of the proposed approach.