Edit distance is a computational grand challenge problem to quantify the minimum number of editing operations required to modify one string of characters to the other, finding many applications of natural language processing. In recent years, relevant and increasing interest has also emerged from deoxyribonucleic acid (DNA) applications, like Next Generation Sequencing and DNA storage technologies. Both applications share two crucial features: i) the information is coded into the four bases of DNA and ii) the level of operational noise is still high causing errors in the data, requiring inclusion in the workflow of the computation of algorithms such as the edit distance for finding similarities between sequences. To boost this computation many solutions are available in the literature. Among them, the FPGAs are largely used since the data domain of those applications is strings of 4 characters represented as two-bit values, inconveniently fitting the basic data types of ordinary CPUs and GPUs, with additional benefits of providing a high level of parallelism and low processing latency. This contribution presents a computing- and energy-efficient design implementing the edit distance algorithm combining metaprogramming and High-Level Synthesis. We also assess the performance of our design targeting recent FPGA-based accelerators. Our solution uses nearly 90% of FPGA basic-block hardware resources achieving about 90% of computing efficiency delivering a maximum throughput of 16.8 TCUPS and an energy efficiency of 46 Mpair/Joule, enabling the use of FPGAs as a new class of accelerators for High Performance Computing in DNA applications. • Computing- and energy-efficient edit distance algorithms running on FPGA accelerators. • Targeting short reads for DNA data storage and long reads for genomics applications. • Combining metaprogramming and HLS to design and optimize C codes for FPGA devices. • Achieving about 90% of computing efficiency and near 90% FPGA resources occupancy. • Delivering a peak throughput of 16.8 TCUPS and an energy efficiency of 46 Mpair/Joule.

Non-binary low-density parity-check (NB-LDPC) codes are known to offer several advantages over their binary counterparts, but the higher complexity, and the resource-hungry nature of decoding algorithms have so far restricted their practical usage. In this paper, we propose a new decoding algorithm for NB-LDPC codes over finite fields of characteristic 2, based on a novel binary expansion of the Q-ary Tanner graph. While it offers substantial complexity gains, simulation results demonstrate that the performance loss of the new algorithm, in comparison to the best known decoder, is quite small. Furthermore, due to being based on a binary graph, it is particularly attractive for hardware implementations. We also suggest a simplified version of the algorithm, which offers even higher gains in complexity.

This paper presents a majority-logic decoding (MLgD) algorithm for non-binary LDPC codes based on a novel expansion of the Tanner graph. The expansion introduced converts the Q-ary graph into a binary one, which makes the new MLgD algorithm more attractive for hardware implementations. Proposed algorithm performs significantly better than the existing MLgD algorithms in the waterfall region, and it shows a much lower error-floor as well. Algorithm only requires integer additions, comparisons, finite field operations and some binary operations. Thus, it offers an effective trade-off between performance and complexity in decoding non-binary LDPC codes.

Over the last 15 years, NAND Flash memories have changed our lives: Flash cards [mainly in the secure digital (SD) form factor] have almost completely replaced photographic films, and USB keys have driven floppy disks to extinction. Lately, thanks to a great tradeoff between cost and performance (i.e., write/read speed), NAND Flash technology has begun fighting against hard disk drives (HDDs) in the form of solid-state drives (SSDs).

NAND Flash memories have changed and keep changing our lives. In the past two decades, NAND-based systems, in the form of Flash cards and USB keys, have replaced films and floppy disks. But disruption did not stop there. Today, NAND is really ubiquitous, as it plays the role of storage element inside smartphones and tablets; even further, it is now expanding its reach because solid-state drives (SSDs), i.e., drives built with several NAND devices, are replacing hard disk drives (HDDs) in more and more applications. To fuel this continuous evolution, NAND has to remain very aggressive in terms of cost per bit. When approaching 10-nm technologies, planar NAND is running out of steam: industry and academia have worked hard on finding a solution to this problem for more than a decade. Three-dimensional integration turned out to be the most promising alternative, and it is now eventually reaching the market. This paper is about 3-D NAND Flash memories and the related integration challenges. Charge trap and floating gate 3-D technologies will be discussed with the aid of several bird's-eye views. Advanced layout techniques will thoroughly be analyzed. Finally, future scaling trends will be presented.

The articles in this special issue cover all the most recent advances in the solid-state drive field from both hardware and software/firmware perspectives. If we look at the DRAM history, DRAM data access speeds have increased at a faster rate than HDDs. The gap in read and write performances between DRAM and HDD has widened in the last years, leaving an opportunity for a new intermediate memory/storage technology between HDDs and DRAM: nand Flash-based SSDs can fill this performance gap, thus profoundly changing the traditional memory hierarchy below the microprocessor.

Solid-state drives (SSDs) faced an astonishing development in the last few years, becoming the cornerstone to new paradigms and markets of the information technology, such as cloud computing and big data centers. So far, the SSD design approach has focused on the optimization of the Flash translation layer, the firmware devoted to fulfill the compatibility with traditional hard-disk drives. For hyperscaled SSDs this strategy is no longer valid since their performance and reliability are strictly linked to that of the NAND Flash memories that constitute the storage medium, in particular when the multilevel cell paradigm is considered. For this reason, the design flow must follow a bottom-up approach that, starting from an accurate knowledge of the time and use dependent reliability of the NAND Flash memories, selects the most appropriate error correction strategy to extend the SSD lifetime while reducing its performance degradation. Then, the design flow moves to that of the SSD controller and of the interface toward the host where the application is running. This paper will thoroughly discuss this bottom-up approach, and finally, it will show how it is possible to leverage new approaches, such as the software-defined storage system that, by exploiting a hardware/software codesign of the SSD controller architecture and of the host application, will be able to revolutionize the traditional computer/memory interaction.

Currently available electronic design automation tools for design space exploration of solid state drives (SSDs) are not able to assess: 1) the device architecture inefficiencies; 2) architecture overdesign for a target performance; and 3) performance degradation caused by the disk usage. These tools feature either an overly high abstraction modeling strategy or lack the required flexibility to perform design exploration. To overcome these problems, this paper proposes SSDExplorer, a tool for fine-grained yet reasonably fast design space exploration of different SSD architectures highlighting possible bottlenecks. To prove its accuracy SSDExplorer has been validated with two real SSDs. SSDExplorer efficiency has been assessed by evaluating the impact of the NAND flash read retry algorithm impact on the SSD performance as a function of its internal architecture.

Solid State Drives (SSDs) are gaining particular momentum in various frameworks such as multimedia, large data centers and cloud environments. Unfortunately, efficient CAD tools for SSD design space exploration able to assess the optimization of the device microarchitecture w.r.t. the target performance are still missing. This paper tries to close this gap by proposing SSDExplorer, a tool for fine-grained and fast design space exploration of SSD devices. SSDExplorer provides unprecedented insights into the architecture behavior and subcomponent interaction efficiency, while avoiding the need for the actual implementation of an FTL or of key hardware components. This is achieved by the introduction of suitable abstractions of the different components. This is confirmed by the thorough validation of SSDExplorer against a commercial SSD device.

Three-dimensional (3-D) integration of systems by vertically stacking and interconnecting multiple materials, technologies, and functional components offers a wide range of benefits, including speed, bandwidth and density increase, power reduction, small form factor, packaging reduction, yield and reliability increase, flexible heterogeneous integration with multifunctionality, and overall cost reduction. A new spectrum of opportunities and challenges arises for integrated system designers, which warrants rethinking and innovations from system design perspectives. By selecting three representative cases, i.e., solid-state data storage, power delivery, and hybrid radio-frequency/optical transceiver for distributed sensor networks, this paper intends to exemplify the potentials of exploiting the benefits of 3-D integration technology from system perspectives.

NAND Flash memory has become the preferred nonvolatile choice for portable consumer electronic devices. Features such as high density, low cost, and fast write times make NAND perfectly suited for media applications where large files of sequential data need to be loaded into the memory quickly and repeatedly. When compared to a hard disk drive, a limitation of the Flash memory is the finite number of erase/write cycles: most of commercially available NAND products are guaranteed to withstand 105programming cycles at most. As a consequence, special care (remapping, bad block management algorithms, etc.) has to be taken when hard-drive based, read/write intensive applications, such as operating systems, are migrated to Flash-memory based devices. One of the basic requirements of the consumer market for data storage is the portability of stored data from one device to the other. Flash cards are the actual solution. A Flash card is a nonvolatile ldquosystem in packagerdquo in which a NAND Flash memory is embedded with a dedicated controller. This paper presents the basic features of the NAND Flash memory and the basic architecture of Flash cards. We provide an outlook on opportunities and challenges of future Flash systems.

The ever-increasing demand for portable equipment is leading to the use of flash memory devices for nonvolatile storage. Fast access time and low power consumption are obviously key requirements. Moreover, multilevel storage techniques are mandatory to reduce the cost per megabit. As a consequence, the READ operation becomes more and more critical, and optimized solutions are needed for almost all circuits involved in the read path. This paper examines the whole read path from addresses to data output, and describes several schemes developed to achieve the required high performances.

In a flash memory, a number of voltage levels different from V/sub DD/ are needed to perform the required operations (read, program, and erase) on the array cells. In the case of single-supply memory devices, voltages higher than V/sub DD/ as well as negative voltages, which are referred to as high voltages (HVs), must be produced on-chip. This paper aims at giving the reader an overview of how HVs are generated and managed in single-supply NOR-type flash memories programmed by channel hot-electron injection. Both schemes used for conventional (i.e., bilevel) memory devices and schemes designed to meet multilevel memory requirements are addressed.