In earlier studies a distributed neural network, referred to as a neuromic array, was introduced. The earlier designs were restricted to binary alphabets. The present study loosens this restriction by demonstrating the design extension to the quartic case. A natural morphism between the quartic valued and binary valued vector spaces is used to establish a design equivalence between the two settings. This correspondence compares the robustness and performance of equivalent binary and quartic designs.>

Linear maps on a 2-D signal space are considered. Using recent results on fast linear transforms, several categories of fast-2-D maps are identified. The connections between fast processing and type of kernel separability are developed. Companion systolic architectures that efficiently realize the fast forms are discussed. The transfer functions of fast 2-D processors are analyzed and illustrated through examples.>

The problem of m-D filtering using sequential scanning is considered. It is shown that the optimal causal filter and the performance measure depend on the scan selected. Examples show that this effect can be significant. Possible techniques to select a suitable scan are analyzed.

The effect of component errors on the behavior of polylogic circuits is considered. A design procedure which minimizes these effects is developed. An example design exhibiting improved performance is presented.

The properties of polynomic functions on Rn are reviewed. Such functions are then used to establish a general synthesis procedure for arbitrary multivalued switching functions. The relationship with threshold logic and Boolean logic is also explored.