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Tomoo Kisaka

dblp:65/4089 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.112005
A watermarking system for IP protection by a post layout incremental router · DAC 2005
Electronic design automation
intellectual property protection		 0.112005
A watermarking system for IP protection by a post layout incremental router · DAC 2005
Electronic design automation › intellectual property protection
watermarking		 0.112005
A watermarking system for IP protection by a post layout incremental router · DAC 2005
Electronic design automation
physical design		 0.012005
A watermarking system for IP protection by a post layout incremental router · DAC 2005
Electronic design automation › physical design
routing		 0.012005
A watermarking system for IP protection by a post layout incremental router · DAC 2005

Methods — techniques the papers use, named apart from their topics

probabilistic rip-up and reroute · 0.1DES encryption · 0.1
YearPublicationVenuePosition
2005 A watermarking system for IP protection by a post layout incremental router
abstract
In this paper, we introduce a new watermarking system for IP protection on post-layout design phase. Firstly the copyright is encrypted by DES (Data Encryption Standard) and then embedded by using an incremental router into the layout design. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated. The incremental router consists of a rip-up and a special re-router that inserts redundant bends into wires probabilistic. We evaluated the technique on various generated benchmark circuits to validate the completeness of the procedure. The results show it achieves almost 100% success for embedding with no extra area cost on design performances.
Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga
 DAC2