Ziyi Guan, Jason Chun Lok Li, Zhijian Hou, Pingping Zhang, Donglai Xu, Yuzhi Zhao, Mengyang Wu, Jinpeng Chen, Thanh-Toan Nguyen, Pengfei Xian, Wenao Ma, Shengchao Qin, Graziano Chesi, Ngai Wong. Proceedings of the 2025 Conference on Empirical Methods in Natural Language Processing. 2025.

With the wide application of Internet of Things (IoT) devices in the power grids, the sophisticated feedback on their operating status is of great significance for improving efficiency and reducing accidents. For exquisite management of the resilient intelligent IoT with flexible increase and decrease of devices and heterogeneous operating systems, this article proposes an adaptive measurement method “MRAM,” which can snapshot the multidimensional resource view (MRV) of all devices in the jurisdiction. Extensible gateway platform based on CPU, field-programmable gate array, and cloud computing is applied in MRAM, which liberates the local resources of monitored IoT devices. MRAM improves the long short-term memory algorithm called ELSTM. ELSTM can accommodate the current IoT devices’ state for detecting the mutation of MRV. The newly collected resources determined by ELSTM whether MRAM enters an abnormal state to drive the adaptive measurement state machine. According to the state machine which endeavors that the MRV is updated timely, MRAM adjusts the measurement granularity in real time. Simulations and experiments have tested the convergence time and occupied bandwidth of MRAM deployed in power grids. These evaluations confirmed MRAM’s practicality and robustness, as well as the MRV is genuine management data for the upper layer power grids applications. A real environment is built to test the performance of this method as well. MRAM has high measurement accuracy and the precision of mutation detection is 98.41%. It converges the update MRV of second level under the condition of IoT devices and the cloud’s low consumption of memory and CPU utilization.

MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than close-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, voltage control readout technique suffers from poor noise performance and low power efficiency (in terms of FoM). In this paper, the weak feedback oversampling successive approximation readout circuit which merges the closed-loop hybrid dynamic amplifier with noise reduction technique is proposed to achieve low noise floor, high power efficiency and high accuracy. The proposed WFB-OSA based readout circuit is fabricated in a commercial$0.18\mu \text{m}$1.8V CMOS process. The measurement result shows that the circuit has achieved a noise floor of$63\mu g/\surd Hz$and an FoM of 14pJ.

MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than closed-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, the voltage control readout technique suffers from low dynamic range and low power efficiency (in terms of$\mathbf {FoM}$). In this paper, the voltage control ratiometric (VCR) readout technique is proposed to improve both dynamic range and power efficiency. The VCR readout technique is demonstrated in a readout circuit fabricated in a commercial 0.18$\mu {\mathrm{ m}}$1.8V/5.0V CMOS process. Compared to the traditional voltage readout circuit fabricated with the same CMOS process and tested with the same sensing element, the VCR readout circuit improves full input signal range by$\mathbf {3.5dB}$(from$\boldsymbol {\pm 8g}$to$\boldsymbol {\pm 12g}$) and the noise floor by$\mathbf {9.5dB}$(from$\mathrm {\mathbf {804~\mu g/}}\sqrt {\mathbf {Hz}} $to$\mathbf {270~\mu g/}\sqrt {\mathbf {Hz}} $). As a result, the dynamic range is improved by$\mathbf {13.0dB}$(from$\mathbf {44.0dB}$to$\mathbf {57.0dB}$), the$\mathbf {Fo}\mathbf {M}_{\mathbf {1}}$is improved from$\mathbf {310pJ}$to$\mathrm {\mathbf {83pJ }}$and the$\mathbf {Fo}\mathbf {M}_{\mathbf {2}}$is improved from$\mathbf {1977~\mu W\cdot \mu g/Hz}$to$\mathbf {796~\mu W\cdot \mu g/Hz}$.

The evolution of new technologies in network community is getting ever faster. Yet it remains the case that prototyping those novel mechanisms on a real-world system (i.e. CPU-FPGA platforms) is both time and labor consuming, which has a serious impact on the research timeliness. In order to bring researchers out of trivial process in prototype development, this paper proposed FAST, a software hardware co-design framework for fast network prototyping. With the programming abstraction of FAST, researchers are able to prototype (using C, verilog or both) a wide spectrum of network boxes rapidly based on all kinds of CPU-FPGA platforms. FAST framework takes care of managing DMA, PCIe and Linux Kernel while providing a unified API for researchers so they can focus only on the packet processing functions. We demonstrate FAST framework's easy to use features with a number of prototypes and show we can get over 10x gains in performance or 1000x better accuracy in clock synchronization compared with their software versions.

Socket buffer (SKB) is the standard data structure for exchanging packets and their control information between NIC driver and protocol stack. The overhead of dynamic SKB management has been considered as the significant bottleneck in packet I/O. Some novel non-SKB mechanisms, such as DPDK, were thus proposed to solve the problem. However, these mechanisms usually cannot be widely adopted in the data path of most packet forwarding applications, due to their incompatibility with SKB. In this paper, a new SKB-compatible mechanism, namely Self-described buffer (SDB), is proposed to improve the efficiency of packet I/O. SDB eliminates SKB allocation/deallocation overhead by offloading SKB management into NIC hardware. It also reduces the overhead of dynamic binding/unbinding operations existed in SKB management by statically binding related information in advance using the free space of Databuf. To evaluate the proposed approach, a SDB-enabled NIC and its driver has been designed and implemented based on FPGA. Experimental results show that the proposed SDB achieves 2× throughput compared with a traditional SKB mechanism in raw packet forwarding, and 34.75% improvement for typical network forwarding applications (e.g. IP forwarding, Bridge forwarding and SDN forwarding) on average.

Learning accurate prior knowledge of natural images is of great importance for single image super-resolution (SR). Existing SR methods either learn the prior from the low/high-resolution patch pairs or estimate the prior models from the input low-resolution (LR) image. Specifically, high-frequency details are learned in the former methods. Though effective, they are heuristic and have limitations in dealing with blurred LR images; while the latter suffers from the limitations of frequency aliasing. In this paper, we propose to combine those two lines of ideas for image super-resolution. More specifically, the parametric sparse prior of the desirable high-resolution (HR) image patches are learned from both the input low-resolution (LR) image and a training image dataset. With the learned sparse priors, the sparse codes and thus the HR image patches can be accurately recovered by solving a sparse coding problem. Experimental results show that the proposed SR method outperforms existing state-of-the-art methods in terms of both subjective and objective image qualities.

It has been widely accepted that real-time implementations of feedback control systems can be susceptible to timing jitters which may be caused by the underlying real-time and/or embedded implementation architecture. Previous experimental studies aimed at quantifying the levels of degradation that may be observed have mainly concentrated upon relatively simple fixed-gain feedback control schemes (e.g. PID) and time-invariant plant. Although some degradation has been observed, most systems have been shown to be surprisingly robust unless driven to extreme limits. In this paper, we study the jitter sensitivity of a real-time embedded implementation of a digital parameter-adaptive control system. The purpose of the study was two-fold; primarily, to obtain empirical data related to jitter sensitivity (as measured by a quadratic performance metric), and secondarily to explore the potential impact of the underlying scheduler choice on system behavior. The findings indicate that the adaptive controller was heavily influenced by sampling jitter, and that the choice of task scheduler had a role to play.

It is well known that the performance of real-time control applications can be seriously degraded by sampling and actuation jitters and delays. This paper describes a simple hybrid-EDF algorithm which may help to ameliorate some of these problems in resource-constrained embedded systems in which the use of simplified and non-preemptive schedulers is required. The algorithm supports a single preemptive time-critical sampling and actuation task, whilst the remaining tasks are executed non-preemptively and have implicit deadlines. The paper develops an efficient schedulability analysis technique for this framework; analysis and an example are given to illustrate the improvement in efficiency over related techniques.

It is well known that the performance of real-time control applications can be affected by many factors, including the choice (and configuration) of the hardware platform and task scheduling algorithm. This paper presents a real-time hardware-in-the-loop simulation tool that simultaneously integrates concepts from control and real-time computing to allow further investigation into these links. It allows the experimental prototyping and analysis of real-time control systems on real hardware - but within a simulated plant environment -and thus allows the potential impacts of hardware and software architecture on control performance and dependability to be evaluated. The structure of the proposed tool is described, along with a preliminary experiment that has been performed to illustrate some of the test facility capabilities.

This paper describes a hybrid object-based video coding scheme that achieves efficient compression by separating moving objects from stationary background and transmitting the shape, motion and residuals for each segmented object. In this scheme, a new content-based object segmentation algorithm is proposed, which does not assume any prior modeling of the objects being segmented. The binarization process, which finds large object regions, is based on a threshold function that calculates block histograms and takes image noise into account. The resultant binary mask is further processed using morphological operations. The motion vectors are estimated inside the change detection mask using block-matching method between two successive frames, and then the dense motion field is estimated using the motion vectors and the Horn-Schunck algorithm.

A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, a full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.

A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.