Instruction caches are usually designed to fetch the whole block from memory in case of a miss. However, the fetched blocks might contain branch instructions which if taken, will render the rest of the block useless. A novel approach is introduced, namely the Precise Control, which fetches only the words of a cache block that are likely to be used. The performance of Precise Control is evaluated and it is shown that it has a positive influence on system performance. Precise Control reduces the words fetched from memory by up to 60%, thus reducing significantly the communication overhead between cache and main memory as well as the total execution time.

Parallel processors reduce the communication overhead problem with the employment of some form of global communication network. This network however, imposes restrictions on the scalability and technological evolution of the parallel processor. In this paper a novel architecture called PiSMA (Parallel Virtual Shared Memory Architecture) is proposed, which consists of a basic substrate, without a network, providing neighborhood connectivity for local communication. The same architecture can be upgraded, by the addition of a global network. The simulated performance of such an upgradable parallel computer is measured with a wide range of parallel applications and fault tolerant issues are discussed. It is found that the substrate connectivity can provide an effective fault tolerant parallel computer for a large class of applications, while the incorporation of a global network broadens the spectrum of applications that can be executed efficiently by the PiSMA architecture.

An experimental ring communication network, the Cambridge Backbone Ring, for integrated computer data, voice, and real-time video applications is described. The network is aimed as a backbone facility for interconnecting groups of Cambridge Fast Ring (CFR) networks in the Cambridge area. Media access control is through the empty slot technique, with transmitting stations filling multiple slots each ring revolution. The network operates on monomode optical fiber and is designed for an eventual line rate of 1000 Mb/s. In the backbone ring architecture, the bandwidth of the fiber-optic channel can be partitioned into a number (currently four) of time division multiplexing (TDM) channels. This enables stations of varying cost and bandwidth to be attached to one network, parameterized by the number of channels a station can use concurrently. The backbone ring architecture achieves full connectivity, even with the simplest type of station. Some brief traffic simulation results are presented.>

In this paper we compare the simulated performance of a family of multiprocessor architectures based on a global shared memory. The processors are connected to the memory through caches that snoop one or more shared buses in crossbar arrangement.

A cache was first used in a commercial computer in 1968,1 and researchers have spent the last 15 years analyzing caches and suggesting improvements. In designing a VLSI instruction cache for a RISC microprocessor we have uncovered four ideas potentially applicable to other VLSI machines. These ideas provide expansible cache memory, increased cache speed, reduced program code size, and decreased manufacturing costs. These improvements blur the habitual distinction between an instruction cache and an instruction fetch unit.