This paper proposes two model predictive current control (MPCC) methods utilizing two output voltages with variable application durations in one sampling period to control the output currents of single-phase voltage source inverters (VSIs). In the proposed methods, the application durations of the two voltages, as well as the selection of two output voltages used in the future sampling period, are determined by an optimization process to minimize current error inside the future sampling period and to eliminate current error at the end of the future sampling instant. By utilizing the two voltages with variable durations, the two proposed MPCC methods can reduce steady-state current errors and decrease output current ripples without increasing the sampling frequency in comparison with the conventional MPCC method, despite only three distinctive output voltages being allowed in the single-phase VSI. The two proposed methods along with the conventional MPCC method are compared in terms of current errors and total harmonic distortion. The effectiveness of the two proposed methods for the single-phase VSIs is verified with both simulation and experimental results.

This paper proposes a novel method to reduce switching losses on the basis of a model-predictive direct power control (MPDPC) method for ac-dc active rectifiers. The main idea is to preselect voltage vectors to decrease switching losses at the next sampling period, and then select one optimum voltage vector among only the preselected voltage vectors to perform direct power control (DPC). The proposed vector preselection scheme enables a predefined cost function to consider only four vectors to control the real and the reactive power at every sampling period. The proposed MPDPC method using only the four preselected vectors stops switching operation of one leg exposed to the largest input current at every sampling period. On the basis of the preselected vectors at each sampling period, the proposed method can effectively reduce the switching losses, as well as accurately perform power control of the active rectifier.

In humans and animals, reward prediction error encoded by dopamine systems is thought to be important in the temporal difference learning class of reinforcement learning (RL). With RL algorithms, many brain models have described the function of dopamine and related areas, including the basal ganglia and frontal cortex. In spite of this importance, how the reward prediction error itself is computed is not understood well, including the problem of how the current states are assigned to a memorized states and how the values of the states are memorized. In this paper, we describe a neocortical model for memorizing state space and computing reward prediction error, known as `reward hierarchical temporal memory' (rHTM). In this model, the temporal relationships among events are hierarchically stored. Using this memory, rHTM computes reward prediction errors by associating the memorized sequences to rewards and inhibits the predicted reward. In a simulation, our model behaved similarly to dopaminergic neurons. We suggest that our model can provide a hypothetical framework of interaction between cortex and dopamine neurons.

Learning invariant representations of environments through experience has been important area of research both in the field of machine learning as well as in computational neuroscience. In the present study, we propose a novel unsupervised method for the discovery of invariants from a single video input based on the learning of the spatio-temporal relationship of inputs. In an experiment, we tested the learning of spatio-temporal invariant features from a single video that involves rotational movements of faces of several subjects. From the results of this experiment, we demonstrate that the proposed system for the learning of invariants based on spatio-temporal continuity can be used as a compelling unsupervised method for learning invariants from an input that includes temporal information.

Leakage power consumption of current CMOS technology is already a great challenge. International Technology Roadmap for Semiconductors projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for CMOS circuits in nanoscale technology. We propose a novel ultra-low leakage CMOS circuit structure which we call "sleepy stack". Unlike many other previous approaches, sleepy stack can retain logic state during sleep mode while achieving ultra-low leakage power consumption. We apply the sleepy stack to generic logic circuits. Although the sleepy stack incurs some delay and area overhead, the sleepy stack technique achieves the lowest leakage power consumption among known state-saving leakage reduction techniques, thus, providing circuit designers with new choices to handle the leakage power problem

In protocol composition techniques, component protocols are combined in various ways to obtain a complex protocol whose execution sequences consist of interleaved execution sequences of the component protocols. We investigate the problem of verifying liveness properties of the composite protocol from the known properties of its components. We first characterize a class of composition techniques that encompasses almost all composition techniques that have appeared in the literature. We then develop a sufficient condition to ensure that certain liveness properties of the component protocols carry over to the composite protocol. A proof technique, based on this sufficient condition, is then used to determine whether the liveness properties of the component protocols also hold for the composite protocol. To demonstrate the usefulness of our technique, we use several protocols including synchronizing, ordering and disabling protocols as examples. The technique is applicable to any transition based protocol model as long as the model is susceptible to reachability analysis for the sake of correctness proofs.

We propose a specification model and present a method to algorithmically derive a protocol specification from a service specification based on the model. Unlike the previous models based on finite state machines, the proposed model can explicitly express concurrency, synchronization, and timing requirements such as delays and timeouts. We assume that there exists a reliable communication channel between say two protocol entities and the maximum delay for each channel is bounded by a positive constant. Because of the variable nature of the communication delays along with the time constraints associated with events, no protocol specification can fully simulate the service specification. The proposed method derives a protocol specification that is optimal in the sense that it provides the largest possible subset of the service specification under the communication delay constraints. We also give a method to derive a sub specification from a service specification and a maximum communication delay of each channel such that the sub specification, but no superset of it, can be simulated by the derived protocol specification.

We propose a framework based on the model of timed extended finite state machines for building communication protocols which perform several functions, where each function corresponds to a component protocol. For parallel composition, we specify a conjunctive relation which requires that the execution of events in two component protocols be synchronized. We also propose a predicate strengthening technique to refine the composite protocol in a stepwise manner while preserving the invariants of the component protocols. For sequential composition, we present a set of constraints, alternating, ordering and disabling, on the actions of the component protocols, and give sufficient conditions for the composite protocol to retain the safety properties such as freedom from unspecified receptions and freedom from deadlocks. Our sufficient conditions are weaker than those given an previous works.