We construct binary dynamic traitor tracing schemes, where the number of watermark bits needed to trace and disconnect any coalition of pirates is quadratic in the number of pirates, and logarithmic in the total number of users and the error probability. Our results improve upon results of Tassa, and our schemes have several other advantages, such as being able to generate all codewords in advance, a simple accusation method, and flexibility when the feedback from the pirate network is delayed.

This paper presents a security architecture for a pay-TV conditional access system, assuming the most challenging scenario from a designer's point of view; a pay-per-view business model in a broadcast-only environment. The starting point for the security architecture is a broadcast encryption scheme and a queueing network for injecting conditional access messages into the broadcast stream. Design constraints related to a conditional access client are taken into account in the design of the architecture, as well as a maximum amount of bandwidth available for the transmission of conditional access messages. In addition, commercial design objectives like quick content access and quick client activation are also addressed. A substantial part of the paper is devoted to the design and analysis of an efficient injector model based on queueing theory, defining the strategy for injecting conditional access messages into the broadcast stream. A numerical example with real-world values of the parameters is used to demonstrate the effectiveness of the presented approach.

This contribution introduces a new class of multipliers for finite fields GF((2/sup n/)/sup 4/). The architecture is based on a modified version of the Karatsuba-Ofman algorithm (KOA). By determining optimized field polynomials of degree four, the last stage of the KOA and the module reduction can be combined. This saves computation and area in VLSI implementations. The new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with KOA-based architectures with separate module reduction. The new multipliers lead to highly modular architectures and are, thus, well suited for VLSI implementations. Three types of field polynomials are introduced and conditions for their existence are established. For the small fields, where n=2,3,...,8, which are of primary technical interest, optimized field polynomials were determined by an exhaustive search. For each field order, exact space and time complexities are provided.