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Xiaodong Liu 0018

dblp:65/622-18 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 2014
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%
Theoretical computer science
1 paper
Computational complexity · 100%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design
0.222011
An integrated algorithm for 3D-IC TSV assignment · DAC 2011
Global routing and track assignment for flip-chip designs · DAC 2010
Electronic design automation › physical design › routing
global routing
0.112010
Global routing and track assignment for flip-chip designs · DAC 2010
Electronic design automation › physical design › routing › multilayer routing
layer assignment
0.112010
Global routing and track assignment for flip-chip designs · DAC 2010

Methods — techniques the papers use, named apart from their topics

shortest path · 0.2min-cost max-flow · 0.2integer linear programming · 0.2bipartite matching · 0.2voronoi diagram · 0.1network flow algorithm · 0.1
YearPublicationVenuePosition
2014 Integrated Algorithm for 3-D IC Through-Silicon Via Assignment
abstract
Through-silicon via (TSV) with flip-chip packaging is a technology that enables vertical integration of silicon dies, forming a single 3-D IC stack. A practical model for preplaced TSV assignment of 3-D nets is proposed for this technology. We prove that the general preplaced 3-D IC TSV assignment problem with more than two dies is NP-complete. An integrated algorithm that combines shortest path search, bipartite matching, min-cost max-flow calculation, and postprocessing is developed. Experimental results using actual testing silicon data demonstrate that our flow achieves good results with reasonable runtime when compared to other existing works.
Xiaodong Liu 0018, Gary K. Yeap, Jun Tao 0001, Xuan Zeng 0001
IEEE Trans. Very Large Scale Integr. Syst.1
2011 An integrated algorithm for 3D-IC TSV assignment
abstract
Through-Silicon Via (TSV) is a technology that enables vertical integration of silicon dies forming a single 3D-IC stack. In this paper, a practical model is proposed for the TSV assignment problem of the stacked-die 3D nets. We present the first work in the literature to prove that the general 3D-IC TSV assignment problem with more than two dies is NP-complete. An efficient heuristic algorithm that combines Shortest Path, Bipartite Matching, Min-cost Max-flow and Integer Linear Programming is developed. Experimental results demonstrate that our flow achieves good quality of results (within 98% of the optimal solution) with reasonable run-time compared to related works.
Xiaodong Liu 0018, Gary K. Yeap, Xuan Zeng 0001
DAC1
2010 Global routing and track assignment for flip-chip designs
abstract
This paper describes a solution for global routing and track assignment of flip-chip I/O nets. Voronoi Diagram (VD) is used to partition the open routing space and the geometrical properties of VD graph are exploited to create global routing channels with capacity and congestion considerations. A network flow algorithm is used to achieve optimal global routing. The regularity of the flip-chip bump placement is observed and allows us to reduce the size of global routing channel graph by over 50% to speed up computation. A track assignment algorithm avoids crossing wires before completing the final route with a detailed router. Experiment results using actual silicon chip data demonstrate that our solution achieves good quality of results compared to an implementation used in a commercial tool.
Xiaodong Liu 0018, Gary K. Yeap, Chunlei Chu, Jian Sun 0005, Xuan Zeng 0001
DAC1