The bit-error rate (BER) performance of a DS-CDMA/QPSK system taking into account the effect of fast fading and high frequency offset is analyzed. The performance is obtained by deriving the SNR of the demodulated signal as a function of the correlation between received signal values and estimated values of the channel estimator. The derived SNR shows that the conventional channel estimator using a single integrator structure has some problems such as the degradation of estimator's performance from fast phase change. We propose a new channel estimator using a double integrator structure that is not affected by fast phase change. We also show the performance comparison between EQOC-QPSK and NEQOC-QPSK data modulation in third generation DS-CDMA. Finally, chip-based simulation is presented to confirm the derived BER performance.

A new lock detection algorithm for digital quadrature phase-shift keying (QPSK) receiver is proposed. Analysis of the detector's output characteristics is given and is verified by using computer simulation. Performance degradation due to carrier jitter is also considered. Analytic and simulation results show that the proposed algorithm is very useful as a lock detector in digital receivers because it has a good detection performance and simple structure.