In the conventional spatial modulation schemes, such as spatial modulation (SM) and quadrature SM (QSM), the number of the transmit antennas must be an integer power of 2, which limits the spectral efficiency and raises the hardware cost. To overcome the antenna limitation, a new modulation method, namely flexible QSM (FQSM), is proposed in this paper. Computer simulation results show that in contrast to the existing SM-like schemes, the proposed FQSM can provide better bit error rate (BER) performance under the same bit per channel use (bpcu). To further make the implementation of the FQSM systems feasible, a low-complexity symbol detection algorithm with matrix merging, group-based Givens rotation, candidate searching, symbol estimation, and likelihood estimation (LE) is introduced. Furthermore, the corresponding very-large-scale integration (VLSI) architecture is also proposed. Finally, the results of simulation and computational complexity reveal that the proposed symbol detection algorithm can offer the near-optimal BER performance with lower computational complexity, compared to other related detection methods. The results of the VLSI architecture implemented under the TSMC 90-nm CMOS technology at an operating frequency of 625 MHz show that the proposed hardware requires 554.37 KGEs and performs a 1562.5 Mbps detection throughput.

In this study, the authors consider symbol detection at the receiver of the base station for uplink massive multiple‐input multiple‐output (MIMO) systems over a fading channel, in which the base station uses a large number of antennas to serve many users. First, the authors review the existing detection methods such as the minimum mean square error and Vertical‐Bell Laboratories Layered Space Time (V‐BLAST). In addition, because the bit error rate (BER) performance of V‐BLAST is close to that of the optimal method, the authors describe the procedures of the V‐BLAST in detail. Then, to achieve a satisfactory trade‐off between the BER performance and the computational complexity for practical implementation in massive MIMO systems, the authors propose a fast group‐based symbol detection scheme. They also derive the expressions needed to select the symbol indices of a group for detection. Our simulation results and complexity analysis show that the performance of the proposed scheme is close to that of the V‐BLAST algorithm with a significant saving in computational complexity.

Fan proposed a set of hyperuniversal switch blocks (HUSBs), called Fan’s (4,${w}$)-HUSBs in this paper. He also proved that his design with${w}$less than 6 was optimum. That is, they used the least switches to achieve hyperuniversal routability. However, we find a counter example to show that there is an unnecessary switch in Fan’s (4, 4)-HUSB. Namely, we propose a new (4, 4)-HUSB, water-molecule-shaped switch block (WMSB), proving (4, 4)-WMSB with 24 switches is optimal. Furthermore, we also propose optimal (4, 7)-WMSB, which is a (4, 7)-HUSB with 42 switches.

Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. This paper presents a novel 128/256/512/1024/1536/2048-point single-path delay feedback (SDF) pipeline FFT processor for long-term evolution and mobile worldwide interoperability for microwave access systems. The proposed design employs a low-cost computation scheme to enable 1536-point FFT, which significantly reduces hardware costs as well as power consumption. In conjunction with the aforementioned 1536-point FFT computation scheme, the proposed design included an efficient three-stage SDF pipeline architecture on which to implement a radix-3 FFT. The new radix-3 SDF pipeline FFT processor simplifies its data flow and is easy to control, and the complexity of the resulting hardware is lower than that of existing structures. This paper also formulated a hardware-sharing mechanism to reduce the memory space requirements of the proposed 1536-point FFT computation scheme. The proposed design was implemented using 90 nm CMOS technology. Postlayout simulation results revealed a die area of approximately 1.44×1.44 mm2with power consumption of only 9.3 mW at 40 MHz.

This paper proposes theories of the design of multi-point interconnection networks, and then develops a switching network scheme which efficiently interconnects FPGAs in Symmetric Programmable Multi-FPGA Systems. A new four-side, hyper-universal switch box is introduced which, satisfying routing resource constraints, is routable for all possible surrounding multi-pin net topologies. This paper proves that when the number of the terminals on each side is greater than 23, the new switch box demonstrates better switch-efficiency than Fan's switch boxes. This paper also presents a formal analysis and extensive experiments on routability comparisons among some of the most well-known FPGA switch boxes such as disjoint switch boxes, Wilton's switch boxes, universal switch boxes, Fan's switch boxes and the new hyper-universal switch networks.

ABSTRACT In wireless mobile computing environments, broadcasting is an effective and scalable technique to disseminate information to a massive number of clients, wherein the energy usage and responsiveness are considered major concerns. Existing air indexing schemes for data broadcast have focused on energy efficiency (reducing tuning time) only. On the other hand, existing broadcast scheduling schemes have aimed at reducing access latency through nonflat data broadcast to improve responsiveness only. Not much work has addressed the energy efficiency and responsiveness issues concurrently. In this paper, we propose a fast data access scheme concurrently supporting energy saving protocol that constructs the broadcast channels according to the access frequency of each type of message in order to improve energy efficiency in mobile devices (MDs). The pinwheel scheduling algorithm (PSA) presented in this paper is used to organize all types of messages in the broadcast channel in the most symmetrical distribution in order to reduce both the tuning and access time. The performance of the proposed mechanism is analyzed, and the improvement over existing methods is demonstrated numerically. The results show that the proposed mechanism is capable of improving both the tuning and access time due to the presence of skewness in the access distribution among the disseminated messages. Copyright © 2011 John Wiley & Sons, Ltd.

This paper demonstrates a multi-band low noise amplifier (LNA) in 0.13µm CMOS process, which is configurable with switching capacitor in 900MHz, 1800MHz, 2.4GHz and 5.2GHz bands. A dual-loop feedback technique is used to enhance the performance in noise figure, power gain and power consumption. The noise figures are 2.6dB at 900MHz, 2dB at 1800MHz, 2.1dB at 2.4GHz and 3.5dB at 5.2GHz; and the power gains are 17dB at 900MHz, 21dB at 1800MHz, 26dB at 2.4GHz and 19dB at 5.2GHz in post-simulation. The S11in all of the bands is below −10dB by wideband matching. The LNA consumes 3.92mW from 1 V supply.

This paper proposes a three-stage rearrangeable polygonal switching network (PSN) for interconnecting one-sided input-output terminals. In comparing our PSN with a three-stage one-sided Clos switching network of the same size and with the same number of switches, we prove that rearrangeability of a PSN is better than that of a Clos switching network. Also, the switching efficiency of the PSN is explored.