The shared last-level cache (SLLC) in heterogeneous multicore system is an important memory component that shared and competitive between multiple cores, so how to improve the SLLC performance has become an important research area. Last-level cache (LLC) bypassing technique that bypasses the LLC a part of memory requests is one of the most effective methods. The bypassed requests are sent directly to off-chip main memory (DRAM) rather than eliminated. We find that the bypassed requests influence the original scheduling sequence in Memory Controller (MC) severely. Besides, immoderate bypassing will disturb the MC load balance. We propose a 3-step method memory that adjusts memory scheduling algorithm to optimize LLC bypassing performance. The first step is adding an independent bypass stream for bypassed requests. The second step is scheduling the bypass stream with a smaller probability than that of normal GPU stream. The third step is adding a guard mechanism for MC. By dynamically set and revoke the guard, we can avoid unbalanced bypassing. For case study, we applied the 3-step method on two modern memory schedulers. The experimental results show that after applied the 3-step method, the schedulers improve the system performance obviously.

Speculative Multi-Threading (SpMT) is a promising technology to harness the growing number of cores in modern CPUs by exploiting the available parallelism out of sequential threads. And with SpMT, the inter-dependent fine-grain threads on different cores need to sync their input and output registers. Inter-core register sync is quite expensive, and heavily impacts the overall performance. We propose a conflict-free scheduling to avoid register read/write conflicts among concurrently executing code blocks. Therefore, while executing, the fine-grain threads do not need to sync the input or output registers with each other. Their output registers are still synced across the cores, but only consumed later. Consequently, the register sync and the execution are decoupled, and the inter-core waiting are eliminated or hidden. However, sometimes the conflict-free scheduling does not perform well when there are insufficient conflict-free code blocks to feed all the available cores. We found that, this problem with conflict-free scheduling could be partially fixed by complementing it with the naive scheduling. Experiments with SPEC2006 showed that in most cases (24 out of 29) the improved scheduling (Hybrid scheduling), i.e. The combination of the conflict-free scheduling and the naive scheduling, significantly out performed the naive scheduling.

Binary translation is used to allow applications of one instruction set architecture (ISA) to run on another, thereby maintaining the binary level compatibility across ISAs. Conventional software binary translation systems suffer performance loss because of architectural heterogeneity amongst ISAs, control flow translation and context switches. In this paper, we propose an FPGA based hardware-software co-designed dynamic binary translation (DBT) system, which moderates these issues at a low level of hardware cost. In our DBT system, we propose a MIPS condition code flags register and a modest ISA extension to bridge the architectural gap, a hardware address mapping mechanism to accelerate the handling of control flow instructions, and a scratchpad memory to reduce performance loss during context switches. We implement the system on Xilinx XC5VLX110T. Quantitative experiments reveal that the overall performance improvement is 56.1% over the baseline configuration, with only extra 1.4% of slices and 5.4% of BRAMs of Xilinx XC5VLX110T occupied.

The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines that are never reused or reused for few times. In this case, the cache performance can be improved through retaining a portion of working set in cache for a period long enough. Previous schemes approach this by bypassing never reused lines. Nevertheless, severely constrained by the number of never reused lines, sometimes they deliver no benefit due to the lack of never reused lines.

As the rapidly development of embedded systems, it is a challenge for universities to fill the gap between education and industry. In this paper, we introduce the experiment designed for embedded system curriculum based on embedded IA first, and then adapt the design to the new promising processor-Atom¿ - developed by Intel. At last, we will share our experiences in the experiment teaching of embedded system.

MEMS-based storage device is a new candidate of storage device for pervasive applications which requires large volume of storage. Because of its attractive features such as high-bandwidth, low-power consumption, and low cost compared with hard disk, the storage performance could be significantly improved by adopting MEMS-based storage devices, especially when employing new request scheduling algorithm and data placement A new request scheduling algorithm is explored for MEMS-based storage devices in this paper, which is named parallelism-aware and zone-based shortest positioning time first (PZSPTF). And a new data placement scheme is also introduced, with which the storage area is divided into 2 parts according to 2 file classes, and the files of same class will be stored in the same part. Experiments show that the new PZSPTF algorithm improves the performance of MEMS storage by 7.83% to 18.51% compared with the widely acknowledged request scheduling algorithm FCFS (first-come, first-served).

In order to cope with the energy challenge emerging with the process of parallelism in embedded storing device, this paper focuses on the static code restructuring of nested loop array accessing related to storing device. Departing the running time of different devices can extend the duration time when it is in low- power state. Experiment shows that power-aware code restructuring can effectively reduce state switching times and extra power wasted. Static method described in this paper can achieve up to 12% power reduction if it cooperates with proper dynamic method.

Embedded system has become one of the most important directions in computer education. Embedded system is at the intersection of control system, command and control, wireless data systems, real-time system and so on. The Computer Rank Examination (CRE) is designed to promote the certification for computer application. In this paper, we describe the efforts on embedded education for CRE including the curriculum design and practice.