An efficient method for constructing checking sequences for strongly connected reduced, synchronous, completely specified, deterministic, sequential machines processing linking homing sequences (LHS) has been described. For machines not possessing an LHS, the only method for constructing a checking sequence requires the use of locating sequences which are often very long. In this correspondence a general method for constructing efficient checking sequences using multiple linking boming sequences instead of locating sequences is presented.

This correspondence provides improvements to the design of checking experiments for sequential machines. Checking experiments can be divided into three parts: an initialization part, a validating part, and a diagnosing part. For synchronous machines not possessing a distinguishing sequence, the longest part of a checking experiment usually is the validating part. Using linking homing sequences as a replacement for locating sequences [1] or valid homing sequences [2], this correspondence shows that the validating part of an experiment can be significantly reduced for such machines.

The majority of the work in the multiple-valued logic (MVL) area has been devoted to the study of various algebras and their properties. One such algebra was proposed by Allen and Givone. This paper is concerned with circuit realizations for this algebra. GaAs MESFET's are used as the basic circuit elements. Several five-valued circuits are proposed including a LITERAL gate, a MAX gate, and a MIN gate. The circuit analysis program SPICE is used to analyze the circuits, and the results are presented.

A model for two-dimensional linear iterative circuits is defined in the form of matrix equations. From the matrix equations, a two-dimensional characteristic function is defined. It is then proved that a matrix satisfies its two-dimensional characteristic function. This property is used to form a diagnostic matrix. Finally, the diagnostic matrix is used in a minimization technique.

This paper fornulates a state-space model for linear iterative circuits having more than one spatial dimension. A new type of matrix operation is introduced that allows treatment of such models in a relatively straightforward manner. Finally, a form for the general response is developed in terms of this new matrix operation.

A method of solving a system of simultaneous equations within a multiple-valued logic algebra is presented.

Abstract—An algebra for switching circuits that may have multiple values is introduced. A minimization technique suitable for computer implementation is then presented.