Advantages of reconfigurable systems and their importance for engineering education are reported in many publications. The paper presents recent results in this area that are achieved within long-term collaboration of two Universities: University of Aveiro in Portugal and Tallinn University of Technology in Estonia. Many alternative curricula have been analyzed and tested, and finally the following two-level strategy has been chosen: 1) an introductive segment on FPGA technology is given within the disciplines on digital design for the first year students; 2) a number of advanced courses, one of which is obligatory and the other optional, are given for the fourth and fifth year students. The paper discusses the methodology that has been developed and successfully realized. We also demonstrate advantages of both the proposed course structure and continuous evaluation with the main objective to disseminate the results.

Zynq-7000 devices from Xilinx incorporate a dual-core processing unit running software, programmable logic that can be customized to implement different hardware circuits, and interfaces enabling interactions and data exchange between software and hardware components to be provided. Such devices permit complete solutions for embedded systems to be integrated on a chip. The paper compares different types of Zynq-based systems and studies communications between the processing unit and the programmable logic. Thorough evaluation of the available on-chip high-performance interfaces is done based on the results of numerous experiments. Two types of projects that are data sorters and popcount computations were chosen for particular assessments. We found that efficiency of software/hardware solutions depends on many mutually related factors such as the volume of processed data, applied parallelism, and involved high-performance ports. Concrete recommendations based on experiments and comparisons are given and discussed.

In this paper we report on recent advances in teaching Field-Programmable Gate Array-based systems within engineering courses given in two Universities: University of Aveiro in Portugal and Tallinn University of Technology in Estonia. Although both institutions have a 6-year history of intensive and fruitful collaboration in this area there is a constant need to update both the teaching methods and the respective laboratory equipment and tools to keep in pace with the demanding industry requirements. This paper describes the most recent changes in the organization of the respective courses and the corresponding teaching materials. In particular, the developed communication modules required for software/hardware co-design are explained in detail.

The paper describes the proposed methodology for teaching reconfigurable (Field-Programmable Gate Array based) systems and international collaboration in education. The methodology includes e-learning tools (namely, tutorials, templates, and previously developed students' projects) combined with another methods that are: separation of given to students tasks on core and auxiliary components, and design based on interactions, virtualization, and communication with host computers. Future directions are also discussed. Numerous examples are presented, including particular cases of teaching outside of home universities. Evaluation of the proposed methodology in a period of three years was also done and the results are presented.

The paper describes the hardware implementation and optimization of algorithms that process tree-like data structures which are needed for numerous practical applications in such areas as databases, embedded systems, and networks requiring priority management. The emphasis is done on applications that involve fast processing of new incoming data items, such as resorting. Parallelism is achieved by constructing N binary trees (N>;1) and applying concurrent operations to N trees at the same time with the aid of N communicating processing modules. It is shown that the considered technique can efficiently be combined with sorting networks, which gives new potentialities for optimization. Modeling in software, experiments with FPGA-based circuits on different computing platforms, and comparisons with the other known methods demonstrate that the performance is increased significantly. It is also shown that the proposed algorithms are easily scalable.

The paper describes the hardware implementation and optimization of sorting algorithms that use data items as memory addresses with one-bit flags indicating presence of data. The proposed technique enables such type of address-based sorting to be applied either directly or through tree-walk tables permitting number of bits in sorted data items to be increased by constructing and traversing N-ary trees (N>;2) composed of so called no-match and working nodes. The latter are organized in well balanced sub-trees of equal depth. It is allowed more than one data item to be assigned to leaves of working sub-trees and such sets of items are processed by fast acceleration circuits. Experiments and comparisons demonstrate that the proposed technique can be used efficiently in low cost FPGAs.

The paper is dedicated to hardware accelerators for data sorting using tree-based recursive algorithms. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model of a hierarchical finite state machine. The paper presents new results in: 1) computational models and hardware architectures; 2) optimization and parallel execution of recursive sorting algorithms; 3) the analysis and comparison of alternative and competitive techniques for implementation of recursive sorting algorithms both in hardware and software. Experiments with the proposed FPGA-based hardware accelerators demonstrate that the performance of sorting operations is increased compared to known implementations.

Reconfigurable systems are widely used nowadays to increase performance of computationally intensive applications. There exist a lot of synthesis tools that automatically generate customized hardware circuits from specifications in both high-level and hardware description languages. However, such tools have a limited applicability because they are unable to handle recursive functions whereas it is known that recursion is a powerful problem-solving method widely used in computer science. Therefore a great deal of research effort is aimed at efficient implementation of recursion in reconfigurable hardware. This paper presents the state of the art in this area. The existing proposals are described, analyzed, and compared according to such criteria as level of parallelism supported, approach to concurrency, ease of use, availability of automated high-level synthesis tools, etc.

This paper discusses an approach for solving combinatorial problems by combining software and dynamically reconfigurable hardware (configware). The suggested technique avoids instance-specific hardware compilation and, as a result, allows obtaining higher performance than currently available pure software approaches as well as instance-specific reconfigurable solutions. Moreover, the technique permits problems to be solved that exceed the resources of the available reconfigurable hardware. The architecture of dynamically reconfigurable hardware problem solver is modeled in software allowing to estimate different characteristics, such as the time of reconfiguration, performance, etc., and to speed up the overall design process.

This paper presents an encoding algorithm that is very efficient for many different logic synthesis problems. The algorithm is based on the use of special tables and includes two basic steps: searching for predefined graphical shapes in the tables, and swapping coded variables in the tables taking into account some constraints. The latter are specified with the aid of an auxiliary graph that reflects the overlap between coded variables in different subsets that have to be accommodated in the tables. The examples in the paper and the results of experiments have shown that the use of the proposed algorithm for state encoding allows the number of logic elements for combinational circuits of finite state machines to be decreased.

The paper discusses an FPGA-based prototyping system with both wired and wireless programming and data exchange facilities. The system can be efficiently used for different types of portable devices. For example, it can supply additional interfaces to mobile computers; can be seen as a hardware accelerator for solving computationally complex problems or serve as a base for portable embedded applications. The system includes an extendable core prototyping board, development tools and supplementary software. The board is designed in such a way that it provides direct support for reconfiguration and self-reconfiguration. It can also be employed for virtual prototyping systems that require more resources that the capacity of the onboard FPGA. The supplementary software includes all necessary drivers and interfaces to interact with the board. The development tools are targeted to design space exploration and they consist of hardware description language libraries, design templates, IP cores, software models and multimedia applications. The latter are mainly used for different types of experiments and for hardware/software partitioning.

This paper describes the advanced real-time processor architecture (ARPA) system-on-chip. The goal of this work is to create a technology independent and synthetizable system-on-chip (SoC) model for real-time applications. The main component of the SoC is a MIPS32-based RISC processor. It is implemented using a pipelined simultaneous multithreading structure that supports the execution of more than one thread or task at a time. The synergy between pipelining and simultaneous multithreading allows combining the exploration of Instruction level parallelism and task level parallelism, hide the context switching time and reduce the need of employing complex speculative execution techniques to improve the performance of the pipelined processor. A fundamental component of the ARPA SoC is the operating system coprocessor, which implements in hardware some of the operating systems functions, such as task scheduling, switching, communication and timing. The proposed architecture allows building flexible, high performance, time predictable and power efficient processors optimized for embedded real-time systems.

The paper analyses and compares alternative iterative and recursive implementations of FPGA circuits for various problems. Two types of recursive calls have been examined, namely for cyclic and binary (N-ary) search algorithms. The details of experiments are presented for four different design problems. The relevant comparative data have been obtained as a result of synthesis and implementation in FPGAs of the respective circuits from system-level (Handel-C) and RTL (VHDL) specifications.

This paper suggests tools that provide significant improvements in the design and verification of FPGA-based digital circuits. These tools include reusable specifications of hardware components (modules) that have been proposed for two types of CAD environments; Xilinx ISE 5.x and Celoxica DK1. The components can be employed to implement both application-specific blocks from the selected area (mainly from the scope of combinatorial computations) and a number of interfaces that are very useful for interaction and data exchange with devices attached to a FPGA, such as LCD and touch panels, bus controllers, etc. The designed modules can be easily integrated into any application-specific digital system and used for visualizing the results, fast data transfer, debugging of internal sub-circuits, etc. They were constructed in such a way that their functionality can be either fixed or modifiable (both statically and dynamically). The latter capability was provided with the aid of reloadable RAM-based blocks. To illustrate the capabilities of the tools suggested, four design examples are discussed. Additional materials for this paper are available in the form of a number of tutorials and projects for FPGAs that can be accessed through the Internet.

This paper suggests a novel architecture for a reconfigurable accelerator for computations over discrete vectors. The number of executed operations is limited but they can arbitrarily be chosen from a practically unlimited set of feasible operations. The software model and hardware implementations of the accelerator are discussed in detail.

The paper discusses some new hardware and software tools that can be used for the design of virtual circuits based on dynamically reconfigurable FPGAs. With the aid of these tools we can implement a system that requires some, hardware resources R/sub c/, on available hardware that has resources R/sub h/, where R/sub c/>R/sub h/. The main idea of the approach supported by these tools is the rational combination of FPGA capabilities with some proposed methods for producing a modifiable specification, together with a novel technique for architectural and logic synthesis, which has been incorporated into the new design environment.

No abstract available.

This paper discusses the behavioral description, logic synthesis, and practical use of control units modeled as hierarchical finite-state machines with virtual states. The technique considered here provides a natural mechanism for top-down decomposition and enables us to develop any complex control algorithm step-by-step, where, at each stage, we are only dealing with a particular level of abstraction. Within any level, the specification encapsulates the control data and functions and allows recursive calls. Finally, the approach enables control units to be designed such that they incorporate new properties such as flexibility and extensibility. The primary functional components of a control algorithm can be reused in future applications.