This paper introduces a novel 3-Dimensional (3D) vertically integrated adaptive computing system. This 3D-SoftChip is a combination of state-of-the-art processing and interconnection technology. It comprises the vertical integration of two chips (a Configurable Array Processor and an Intelligent Configurable Switch) through indium bump 3D interconnections. The Configurable Array Processor (CAP) is an array of heterogeneous processing elements (PEs) while the Intelligent Configurable Switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer along with a Direct Memory Access (DMA) controller. This paper introduces the 3D-Softchip architecture for real-time communication and multimedia signal processing as a next generation computing system and describes the HW/SW codesign and verification methodology using SystemC.

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Abstract — We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-based contention algorithm is proposed, modeling in VHDL for high-speed cell scheduler of ATM switching. A digital hopfield neural cell scheduler which has the ability of real-time processing is used to solve loss of throughput due to head-ofline(HOL) and internal blocking when FIFO queueing is employed at the Banyan network. In this scheduler, it is found we can minimize the delay for scheduling and select nonblocking cells in maximum leading to high performance. Our proposed ATM switch is modeled in VHDL, synthesized, implemented into a FPGA chip set and fabricated using 0.6 CMOS technology. I.

We developed a Video Multi Processor (VMP) for image compression and decompression schemes of MPEG (especially MPEG-2) in this study. The VMP would apply to programmable architecture, various flexibilities to implement real-time image compression algorithm, and other many applications such as DVD-CD ROM authoring tool and videophone/teleconferencing systems. IO architecture of the VMP is designed for the multi-processor functionality in which uses many VMPs according to required arithmetic quantities of the system. Further, the architecture of the VMP system is simplified by processing the necessary peripheral IO system operations within the processor.