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VLDB 2026 Research / reviewers in the wild / expert

K.-T. Tran

dblp:66/4896 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 82% Performance modeling and evaluation · 18%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › debugging
design debugging		 0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Electronic design automation › hardware verification and test
diagnosis		 0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Electronic design automation › hardware verification and test
formal verification		 0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Electronic design automation
hardware verification and test		 0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Performance modeling and evaluation › simulation › analog and hybrid computer simulation
hybrid simulation		 0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Electronic design automation
hardware description language		 0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989
Electronic design automation › hardware description language
VHDL		 0.011989
VVDS: A Verification/Diagnosis System for VHDL · DAC 1989

Methods — techniques the papers use, named apart from their topics

symbolic execution · 0.0micro-probing · 0.0
YearPublicationVenuePosition
1989 VVDS: A Verification/Diagnosis System for VHDL
abstract
In this paper, an interactive verification and diagnosis system for VHDL [Vm88], VVDS, is presented. In VVDS, hybrid simulation, which simulates with both numerical and symbolic data, is implemented to achieve an effective compromise of the enormous quantity of input test data in the conventional simulation and the complexity of symbolic expression in the symbolic execution. To support efficient user interface in the verification and diagnosis process, both on-line programming of commands and micro-probing capability to passively and actively probe any level of design hierarchy are provided.
Heh-Tyan Liaw, K.-T. Tran, Chen-Shang Lin
 DAC2