Our motivation for this research is twofold. Firstly, we embed the watermark in wavelet domain rather than DCT domain motivated by the fact that the wavelet transform is used in jpeg2000 standardization process. Secondly, high bit rate watermarks tend to get destroyed, even before between 10% to 32% average lossless compression. Hence we intend to get the watermark detection quality decreasing as we increase the compression ratio to improve detection performance. We will do this by introducing the concept of multiresolution watermark channels. We will develop techniques to construct such watermark channels.

Human facial feature detection is a significant but difficult task. An algorithm of knowledge based eye detection is presented. The algorithm consists of two main stages: the face and eye region locating stage and the eye detection stage. In the first stage, an effective approach to fast location of the face and eye region is developed. In the second stage, eye edge contour searching directed by knowledge is introduced in detail. Regional image processing techniques are also described in the second stage. The main purpose of the first stage is to locate the eye region roughly. The algorithm employed in the second stage is restricted to application in just this region. It reduces the complexity of the first stage and improves the reliability in the second stage. The Yale Face Database is used to evaluate the capability of the proposed methods and the results are promising.

Many applications in signal and image processing can be efficiently implemented on regular VLSI architectures such as systolic arrays. Multirate arrays (MRAs) are an extension of systolic arrays where different data streams are propagated with different clocks. We address the analysis and synthesis problem for this class of architectures. We present a formal definition of MRAs, as systems of recurrence equations defined over sparse polyhedral domains. We also give transformation rules for this class of recurrences, and use them to show that MRAs constitute a particular subset of systems of affine recurrence equations (SoAREs). We then address the synthesis problem, and show how an MRA can be systematically derived from an initial specification in the form of a mathematical equation. The main transformations that we use are domain rescalings and dependency decomposition, and we illustrate our method by deriving a hitherto unknown decimation filter array.

Many applications in signal and image processing can be implemented on regular VLSI architectures such as systolic arrays. Multirate arrays, or MRAs are an extension of systolic arrays where different data streams propagate with different clocks. It is known that they can be modelled as systems of uniform recurrence equations over sparse polyhedral domains. Using well known linear index transformation rules for systems of affine recurrence equations, or SAREs, we show that MRAs constitute a particular proper subset of SAREs. We describe how an MRA can be systematically derived from an initial specification in the form of a mathematical equation. The main transformation that we use is dependency decomposition, and rue illustrate our method by deriving a hitherto unknown decimation filter array that improves upon the hardware cost of previously published filters.

This paper describes a unified approach to checking data link and computational conflicts in mapping algorithms to lower-dimensional processor arrays. Based primarily on the notion of Hermite normal form, we propose a range of necessary and sufficient conditions to identify mappings without data link and computational conflicts. These conditions are then used to find optimal time mappings of a transitive closure algorithm to linear processor arrays.

We present PMC-3D, a parallel three-dimensional (3-D) Monte Carlo device simulator for multiprocessors. The parallel algorithm is an extension of the standard Monte Carlo device simulation model in 3-D, in which the particle dynamics generated from the stochastic Monte Carlo method are solved simultaneously with Poisson's equation on a 3-D mesh using finite differences. Due to the large computational requirements of 3-D device simulation, it is necessary to parallelize both the Poisson solver and the Monte Carlo simulation phase of the device simulator. The parallel algorithms were implemented on a 1024-node distributed memory nCUBE multicomputer and a 4-mode shared memory Ardent multiprocessor. We validate the accuracy of our implementations by generating the static characteristics of a MESFET and present test results on the fixed and scaled speedups obtained on the two types of parallel computers. Improvements in performance are observed utilizing dynamic load balancing for the distributed memory case.>

Single-read-single-write (SRSW) variables are presented for synchronous and asynchronous communication between processes. The operational semantics of the instruction accessing these variables is quite simple: a SRSW variable can be written if it is free, and, once written, it becomes busy. A SRSW variable can be read when busy, and, once read, it becomes free. A process attempting to read a free SRSW variable or write a busy SRSW variable is put in a wait state until the state of the variable changes. The advantages of SRSW variables are multiple. The syntax of a regular sequential language can be used without any change, other than the introduction of a new SRSW data type. Parallel programs tend to be concise and easy to prove correct. The message passing paradigm can be very easily modeled with SRSW variables.>

Bidirectional message-passing (bi-io), a novel symmetric communication mechanism for concurrent processes, is introduced and developed. The mechanism is symmetric in the sense that, in one atomic action, a message is transmitted in each direction between two processes. For some applications (tree structure, systolic arrays) this method is shown to have several advantages over conventional synchronization and communication primitives (mainly conciseness of programs, absence of certain types of deadlock). The mechanism is rigorously defined with a CSP-like syntax and a weakest-precondition semantics. Two systolic arrays are developed using bidirectional message-passing: a matrix-vector multiplier and a palindrome recognizer.>