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Koji Ara

dblp:66/6247 · DBLP profile ↗
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6ranked-venue papers
3as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-authorHuman-computer interaction and ubiquitous computing · 2Computer networks · 1Software engineering, systems software and programming languages · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 69% Embedded and real-time systems · 24% Energy-efficient computing · 7%
Computer networks
1 paper
Internet of things and sensor networks · 100%

Topics — the 5 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
coverage-driven verification
0.112005
Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Electronic design automation
hardware verification and test
0.112005
Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Electronic design automation › hardware verification and test › functional verification
logic verification
0.112005
Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Energy-efficient computing
low-power design
0.012006
A 15 - 15 mm, 1 µA, reliable sensor-net module: enabling application-specific nodes · IPSN 2006
Electronic design automation › hardware verification and test
processor verification
0.012005
Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005

Methods — techniques the papers use, named apart from their topics

variable transactor · 0.1reactive transactor adaptation · 0.1
YearPublicationVenuePosition
2017 Effect of personal data aggregation method on estimating group stress with wearable sensor: Consideration of group dynamics in workplaces
abstract
In this paper, we evaluate methods of aggregating personal sensor data to estimate the degree of group stress. We compare the estimation accuracy of two aggregation methods, one without and one with personal distribution scaling. As a result of applying the data of 9 groups of people (105 people) to the methods, it is shown that the no-scaling method successfully estimates the degree of group stress better than the other (average error = 1.19, r = 0.964). At the conclusion of discussion, it is suggested that the method without scaling is valid because both the group stress state and method reflect the interaction among people.
Satomi Tsuji, Nobuo Sato, Koji Ara, Kazuo Yano
SMC3
2011 Healthcare of an organization: Using wearable sensors and feedback system for energizing workers
abstract
A badge-shaped sensor and feedback system were developed. This system makes it possible to study human and organizational behavior in an office. By prompting changes in workers' behavior, it improves productivity as well as helps to solve individual's problems. Aiming to improve the productivity and quality of project management, the system was applied at a software development company. The results show that the system can improve the human communication process, as well as motivate workers by giving them the chance to reflect on their work styles and to help their colleagues.
Koji Ara, Tomoaki Akitomi, Nobuo Sato, Satomi Tsuji, Miki Hayakawa, Yoshihiro Wakisaka, Norio Ohkubo, Rieko Otsuka, Fumiko Beniyama, Norihiko Moriwaki, Kazuo Yano
ASP-DAC1
2009 Sensible Organizations: Technology and Methodology for Automatically Measuring Organizational Behavior
abstract
We present the design, implementation, and deployment of a wearable computing platform for measuring and analyzing human behavior in organizational settings. We propose the use of wearable electronic badges capable of automatically measuring the amount of face-to-face interaction, conversational time, physical proximity to other people, and physical activity levels in order to capture individual and collective patterns of behavior. Our goal is to be able to understand how patterns of behavior shape individuals and organizations. By using on-body sensors in large groups of people for extended periods of time in naturalistic settings, we have been able to identify, measure, and quantify social interactions, group behavior, and organizational dynamics. We deployed this wearable computing platform in a group of 22 employees working in a real organization over a period of one month. Using these automatic measurements, we were able to predict employees' self-assessments of job satisfaction and their own perceptions of group interaction quality by combining data collected with our platform and e-mail communication data. In particular, the total amount of communication was predictive of both of these assessments, and betweenness in the social network exhibited a high negative correlation with group interaction satisfaction. We also found that physical proximity and e-mail exchange had a negative correlation of r = -0.55 (p 0.01), which has far-reaching implications for past and future research on social networks.
Daniel Olguín Olguín, Benjamin N. Waber, Taemie Jung Kim, Akshay Mohan, Koji Ara, Alex Pentland
IEEE Trans. Syst. Man Cybern. Part B5
2006 A 15 - 15 mm, 1 µA, reliable sensor-net module: enabling application-specific nodes
abstract
An ultra-small, low-power sensor-net module called ZN1 is developed. ZN1 integrates MCU, ZigBee RF into an ultra-small 15 -- 15-mm module with an ultra-low standby current less than 1 μA. The and highly reliable operation for more than 15 years of the ZN1 enable low-cost practical application-specific sensor nodes for HVAC, structure monitoring, office management, security, medicine, and healthcare. We describe architecture and technologies for developing the ZN1 module. Moreover, we demonstrate two applications that we developed simultaneously: food sanitation and home healthcare. We also show results of the ZN1 module evaluation and discuss reliability of the ZN1.
Shunzo Yamashita, Takanori Shimura, Kiyoshi Aiki, Koji Ara, Yuji Ogata, Isamu Shimokawa, Takeshi Tanaka, Hiroyuki Kuriyama, Kazuyuki Shimada, Kazuo Yano
IPSN4
2005 Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level
abstract
Maintaining coverage with increasing circuit scale has become a critical problem for logic-verification processes. While transaction-level verification (TLV) is an important step forward, fine-grained (FG) TLV provides better signal-level coverage by reactively changing transactors instead of transaction-level scenarios. Evaluations with a microprocessor design show the effectiveness of FGTLV; all design bugs at the signal level were to be detected, though many were not detected by plain TLV.
Koji Ara, Kei Suzuki
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2003 A Proposal for Transaction-Level Verification with Component Wrapper Language
abstract
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simulation-coverage analyzer This approach combines the conventional transaction level language such as C and the signal level language based on our previously developed Component Wrapper Language (CWL). This approach is based on two concepts. The first one is a complete separation between transaction-level verification and signal-level verification for generating suitable verification suites in each design phase. The second one is the quick generation of signal-level verification suites from the original specification written in CWL. Experimental results show that our approach should yield much shorter verification periods versus conventional methods.
Koji Ara, Kei Suzuki
DATE1